MC68HC912B32MFU8 MOTOROLA [Motorola, Inc], MC68HC912B32MFU8 Datasheet - Page 70

• Manufacturer Part Number: MC68HC912B32MFU8
• Description: 16-Bit Microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

PWDTYx — PWM Channel Duty Registers
PWCTL — PWM Control Register
PSWAI — PWM Halts while in Wait Mode
CENTR — Center-Aligned Output Mode
RDPP — Reduced Drive of Port P
PUPP — Pull-Up Port P Enable
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MOTOROLA
PWDTY0
PWDTY1
PWDTY2
PWDTY3
RESET:
RESET:
Read and write anytime.
The value in each duty register determines the duty of the associated PWM channel. When the duty
value is equal to the counter value, the output changes state. If the register is written while the channel
is enabled, the new value is held in a buffer until the counter rolls over or the channel is disabled. Read-
ing this register returns the most recent value written.
If the duty register is greater than or equal to the value in the period register, there will be no duty change
in state. If the duty register is set to $FF the output will always be in the state which would normally be
the state opposite the PPOLx value.
Left-Aligned-Output Mode (CENTR = 0):
Duty cycle = [(PWDTYx
Duty cycle = [(PWPERx
Center-Aligned-Output Mode (CENTR = 1):
Duty cycle = [(PWPERx
Duty cycle = [(PWDTYx
Read and write anytime.
To avoid irregularities in the PWM output mode, write the CENTR bit only when PWM channels are dis-
abled.
0 = Allows PWM main clock generator to continue while in wait mode.
1 = Halt PWM main clock generator when the part is in wait mode.
0 = PWM channels operate in left-aligned output mode
1 = PWM channels operate in center-aligned output mode
0 = All port P output pins have normal drive capability.
1 = All port P output pins have reduced drive capability.
0 = All port P pins have an active pull-up device disabled.
1 = All port P pins have an active pull-up device enabled.
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
0
0
0
6
6
6
6
6
0
6
0
0
1) (PWPERx
1) (PWPERx
PWDTYx) (PWPERx
PWDTYx) (PWPERx
5
5
5
5
5
0
5
0
0
PSWAI
4
4
4
4
4
0
1)]
1)]
4
0
100%
100%
CENTR
1)]
1)]
3
3
3
3
3
0
3
0
100%
100%
RDPP
2
2
2
2
2
0
2
0
(PPOLx = 1)
(PPOLx = 0)
(PPOLx = 1)
(PPOLx = 0)
PUPP
1
1
1
1
1
0
1
0
MC68HC912B32TS/D
PSBCK
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
MC68HC912B32
0
0
$0050
$0051
$0052
$0053
$0054