MC68HC912B32MFU8 MOTOROLA [Motorola, Inc], MC68HC912B32MFU8 Datasheet - Page 35

• Manufacturer Part Number: MC68HC912B32MFU8
• Description: 16-Bit Microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

NDBE — No Data Bus Enable
PIPOE — Pipe Signal Output Enable
NECLK — No External E Clock
LSTRE — Low Strobe (LSTRB) Enable
RDWE — Read/Write Enable
MC68HC912B32
MC68HC912B32TS/D
In special single-chip mode, the E clock is enabled as a timing reference and the other bits of port E are
configured for general-purpose I/O.
In normal expanded modes, the reset vector is located in external memory. The E clock may be required
for this access but R/W is only needed by the system when there are external writable resources. There-
fore in normal expanded modes, only the E clock is configured for its alternate bus control function and
the other bits of port E are configured for general-purpose I/O. If the normal expanded system needs
any other bus-control signals, PEAR would need to be written before any access that needed the addi-
tional signals.
In special expanded modes, IPIPE1, IPIPE0, E, R/W, and LSTRB are configured as bus-control signals.
In peripheral mode, the PEAR register is not accessible for reads or writes.
Read and write anytime.
Normal: write once; Special: write anytime except the first time. Read anytime. This bit has no effect in
single chip modes.
In expanded modes, writes to this bit have no effect. E clock is required for de-multiplexing the external
address; NECLK will remain zero in expanded modes. NECLK can be written once in normal single-
chip mode and can be written anytime in special single chip mode. The bit can be read anytime.
Normal: write once; Special: write anytime except the first time. Read anytime. This bit has no effect in
single-chip modes or normal expanded narrow mode.
LSTRB is used during external writes. After reset in normal expanded mode, LSTRB is disabled. If
needed, it should be enabled before external writes. External reads do not normally need LSTRB be-
cause all 16 data bits can be driven even if the MCU only needs eight bits of data.
TAGLO is a shared function of the PE3/LSTRB pin. In special expanded modes with LSTRE set and the
BDM instruction tagging on, a zero at the falling edge of E tags the instruction word low byte being read
into the instruction queue.
Normal: write once; Special: write anytime except the first time. Read anytime. This bit has no effect in
single-chip modes.
R/W is used for external writes. After reset in normal expanded mode, it is disabled. If needed it should
be enabled before any external writes.
0 = PE7 is used for external control of data enables on memories.
1 = PE7 is used for general-purpose I/O.
0 = PE[6:5] are general-purpose I/O.
1 = PE[6:5] are outputs and indicate the state of the instruction queue.
0 = PE4 is the external E-clock pin subject to the following limitation: In single-chip modes, PE4 is
1 = PE4 is a general-purpose I/O pin.
0 = PE3 is a general-purpose I/O pin.
1 = PE3 is configured as the LSTRB bus-control output, provided the MCU is not in single chip or
0 = PE2 is a general-purpose I/O pin.
1 = PE2 is configured as the R/W pin. In single-chip modes, RDWE has no effect and PE2 is a gen-
general-purpose I/O unless NECLK = 0 and either IVIS = 1 or ESTR = 0. A 16-bit write to
PEAR:MODE can configure all three bits in one operation.
normal expanded narrow modes.
eral-purpose I/O pin.
MOTOROLA
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