MC68HC912B32MFU8 MOTOROLA [Motorola, Inc], MC68HC912B32MFU8 Datasheet - Page 18
MC68HC912B32MFU8
Manufacturer Part Number
MC68HC912B32MFU8
Description
16-Bit Microcontroller
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC912B32MFU8.pdf
(128 pages)
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18
MOTOROLA
Port Name
PDLC[6:0]
Port DLC
PAD[7:0]
Port AD
PA[7:0]
PB[7:0]
PE[7:0]
PP[7:0]
PS[7:0]
PT[7:0]
Port A
Port B
Port E
Port P
Port S
Port T
26–29, 35–38
79, 80, 1–6
16–12, 9–7
Numbers
46–39
25–18
58–51
70–76
68–61
Pin
Table 6 MC68HC912B32 Port Description Summary
DD Register (Address)
DDRDLC ($00FF)
Data Direction
DDRS ($00D7)
DDRT ($00AF)
DDRA ($0002)
DDRB ($0003)
DDRE ($0009)
DDRP ($0057)
PE[7:2] In/Out
PE[1:0] In
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In
Port A and port B pins are used for address and data in ex-
panded modes. The port data registers are not in the address
map during expanded and peripheral mode operation. When
in the map, port A and port B can be read or written any time.
DDRA and DDRB are not in the address map in expanded or
peripheral modes.
Analog-to-digital converter and general-purpose I/O.
Byte Data Link Communication (BDLC) subsystem and
general-purpose I/O.
Mode selection, bus control signals and interrupt service
request signals; or general-purpose I/O.
General-purpose I/O. PP[3:0] are use with the pulse-width
modulator when enabled.
Serial communications interface and serial peripheral in-
terface subsystems and general-purpose I/O.
General-purpose I/O when not enabled for input capture and
output compare in the timer and pulse accumulator sub-
system.
Description
MC68HC912B32TS/D
MC68HC912B32
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