MC68HC912B32MFU8 MOTOROLA [Motorola, Inc], MC68HC912B32MFU8 Datasheet - Page 27

• Manufacturer Part Number: MC68HC912B32MFU8
• Description: 16-Bit Microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

MC68HC912B32
MC68HC912B32TS/D
SMODN, MODB, MODB — Mode Select Special, B and A
ESTR — E Clock Stretch Enable
IVIS — Internal Visibility
EBSWAI — External Bus Module Stop in Wait Control
MODE — Mode Register
RESET:
RESET:
RESET:
RESET:
RESET:
RESET:
RESET:
MODE controls the MCU operating mode and various configuration options. This register is not in the
map in peripheral mode.
These bits show the current operating mode and reflect the status of the BKGD, MODB and MODA input
pins at the rising edge of reset.
Read anytime. SMODN may only be written if SMODN = 0 (in special modes) but the first write is ig-
nored; MODB, MODA may be written once if SMODN = 1; anytime if SMODN = 0, except that special
peripheral and reserved modes cannot be selected.
Determines if the E Clock behaves as a simple free-running clock or as a bus control signal that is active
only for external bus cycles. ESTR is always one in expanded modes since it is required for address
demultiplexing and must follow stretched cycles.
Normal modes: write once; Special modes: write anytime, read anytime.
This bit determines whether internal ADDR/DATA, R/W, and LSTRB signals can be seen on the bus
during accesses to internal locations. In special expanded narrow mode, it is possible to configure the
MCU to show internal accesses on an external 16-bit bus. The IVIS control bit must be set to one. When
the system is configured this way, visible internal accesses are shown as if the MCU was configured for
expanded wide mode but normal external accesses operate as if the bus was in narrow mode. In normal
expanded narrow mode, internal visibility is not allowed and IVIS is ignored.
Normal modes: write once; Special modes: write anytime EXCEPT the first time. Read anytime.
This bit controls access to the external bus interface when in wait mode. The module will delay before
shutting down in wait mode to allow for final bus activity to complete.
0 = E never stretches (always free running).
1 = E stretches high during external access cycles and low during non-visible internal accesses.
0 = No visibility of internal bus operations on external bus
1 = Internal bus operations are visible on external bus
0 = External bus and registers continue functioning during wait mode.
1 = External bus is shut down during wait mode.
SMODN
Bit 7
1
1
0
0
0
1
0
MODB
6
0
1
0
1
1
0
0
MODA
5
1
1
1
1
0
0
0
ESTR
4
1
1
1
1
1
1
1
IVIS
3
0
0
1
1
1
0
1
EBSWAI
2
0
0
0
0
0
0
0
1
0
–
–
–
–
–
–
–
EME
Bit 0
0
0
1
1
1
0
1
MOTOROLA
Normal Exp
Normal Exp
Special Exp
Special Exp
Single Chip
Single Chip
Peripheral
Narrow
Narrow
Normal
Special
Wide
Wide
$000B
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