MC68HC912B32MFU8 MOTOROLA [Motorola, Inc], MC68HC912B32MFU8 Datasheet - Page 75

• Manufacturer Part Number: MC68HC912B32MFU8
• Description: 16-Bit Microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

TCNT — Timer Count Register
TSCR — Timer System Control Register
TEN — Timer Enable
TSWAI — Timer Stops While in Wait
TSBCK — Timer Stops While in Background Mode
TFFCA — Timer Fast Flag Clear All
TQCR — Reserved
MC68HC912B32
MC68HC912B32TS/D
RESET:
RESET:
RESET:
When the OC7Mn bit is set, a successful OC7 action will override a successful OC[6:0] compare action
during the same cycle; therefore, the OCn action taken will depend on the corresponding OC7D bit.
A full access for the counter register should take place in one clock cycle. A separate read/write for high
byte and low byte will give a different result than accessing them as a word.
Read anytime.
Write has no meaning or effect in the normal mode; only writable in special modes (SMODN = 0).
The period of the first count after a write to the TCNT registers may be a different size because the write
is not synchronized with the prescaler clock.
Read or write anytime.
If for any reason the timer is not active, there is no 64 clock for the pulse accumulator since the E 64
is generated by the timer prescaler.
0 = Disables the timer, including the counter. Can be used for reducing power consumption.
1 = Allows the timer to function normally.
0 = Allows the timer to continue running during wait.
1 = Disables the timer when the MCU is in the wait mode. Timer interrupts cannot be used to get
0 = Allows the timer to continue running while in background mode.
1 = Disables the timer whenever the MCU is in background mode. This is useful for emulation.
0 = Allows the timer flag clearing to function normally.
1 = For TFLG1($8E), a read from an input capture or a write to the output compare channel ($90–
the MCU out of wait.
$9F) causes the corresponding channel flag, CnF, to be cleared. For TFLG2 ($8F), any access
to the TCNT register ($84, $85) clears the TOF flag. Any access to the PACNT register ($A2,
$A3) clears the PAOVF and PAIF flags in the PAFLG register ($A1). This has the advantage of
eliminating software overhead in a separate clear sequence. Extra care is required to avoid ac-
cidental flag clearing due to unintended accesses.
Bit 15
Bit 7
Bit 7
Bit 7
TEN
Bit 7
0
0
0
0
TSWAI
14
6
6
0
6
0
6
0
0
TSBCK
13
5
5
0
5
0
5
0
0
TFFCA
12
4
4
0
4
0
4
0
0
11
3
3
0
3
0
0
3
0
0
10
2
2
0
2
0
0
2
0
0
1
9
1
0
1
0
0
1
0
0
Bit 0
Bit 8
Bit 0
Bit 0
Bit 0
0
0
0
0
0
$0084–$0085
MOTOROLA
$0086
$0087
75