MC68HC912B32MFU8 MOTOROLA [Motorola, Inc], MC68HC912B32MFU8 Datasheet - Page 109

• Manufacturer Part Number: MC68HC912B32MFU8
• Description: 16-Bit Microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

ATDCTL1 — Reserved
ATDCTL2 — ATD Control Register 2
AFFC — ATD Fast Flag Clear All
ASWAI — ATD Stop in Wait Mode
ASCIE — ATD Sequence Complete Interrupt Enable
ASCIF — ATD Sequence Complete Interrupt
ATDCTL3 — ATD Control Register 3
FRZ1, FRZ0 — Background Debug (Freeze) Enable (suspend module operation at breakpoint)
MC68HC912B32
MC68HC912B32TS/D
ADPU — ATD Disable
RESET:
RESET:
RESET:
The ATD control register 2 and 3 are used to select the power up mode, interrupt control, and freeze
control. Writes to these registers abort any current conversion sequence.
Read or write anytime except ASCIF bit, which cannot be written.
Bit positions ATDCTL2[4:2] and ATDCTL3[7:2] are unused and always read as zeros.
Software can disable the clock signal to the ATD converter and power down the analog circuits to re-
duce power consumption. When reset to zero, the ADPU bit aborts any conversion sequence in
progress. Because the bias currents to the analog circuits are turned off, the ATD requires a period of
recovery time to stabilize the analog circuits after setting the ADPU bit.
Cannot be written in any mode.
When debugging an application, it is useful in many cases to have the ATD pause when a breakpoint
is encountered. These two bits determine how the ATD will respond when background debug mode be-
comes active.
0 = Disables the ATD, including the analog section for reduction in power consumption.
1 = Allows the ATD to function normally.
0 = ATD flag clearing operates normally (read the status register before reading the result register
1 = Changes all ATD conversion complete flags to a fast clear sequence. Any access to a result
0 = ATD continues to run when the MCU is in wait mode
1 = ATD stops to save power when the MCU is in wait mode
0 = Disables ATD interrupt
1 = Enables ATD interrupt on sequence complete
0 = No ATD interrupt occurred
1 = ATD sequence complete
to clear the associate CCF bit).
register (ATD0–7) will cause the associated CCF flag to clear automatically if it was set at the
time.
ADPU
Bit 7
Bit 7
Bit 7
0
0
0
0
0
AFFC
6
0
0
6
0
6
0
0
ASWAI
5
0
0
5
0
5
0
0
4
0
0
4
0
0
4
0
0
3
0
0
3
0
0
3
0
0
2
0
0
2
0
0
2
0
0
ASCIE
FRZ1
1
0
0
1
0
1
0
ASCIF
FRZ0
Bit 0
Bit 0
Bit 0
0
0
0
0
MOTOROLA
$0061
$0062
$0063
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