MC68HC912B32MFU8 MOTOROLA [Motorola, Inc], MC68HC912B32MFU8 Datasheet - Page 84

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MC68HC912B32MFU8

Manufacturer Part Number
MC68HC912B32MFU8
Description
16-Bit Microcontroller
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
13.2.1 Data Format
84
MOTOROLA
INTERNAL
LOGIC
The serial data format requires the following conditions:
TO
• An idle-line in the high state before transmission or reception of a message.
• A start bit (logic zero), transmitted or received, that indicates the start of each character.
• Data that is transmitted or received least significant bit (LSB) first.
• A stop bit (logic one), used to indicate the end of a frame. (A frame consists of a start bit, a char-
• A BREAK is defined as the transmission or reception of a logic zero for one frame or more.
• This SCI supports hardware parity for transmit and receive.
DATA BUS
acter of eight or nine data bits and a stop bit.)
SC0BD/SELECT
DIVIDER
Figure 20 Serial Communications Interface Block Diagram
MCLK
DETECT
PARITY
SC0CR1/SCI CTL 1
BAUD RATE
CLOCK
Tx Baud Rate
Rx Baud Rate
INT REQUEST LOGIC
SC0SR1/INT STATUS
SC0CR1/SCI CTL 1
DATA RECOVERY
INT REQUEST LOGIC
GENERATOR
PARITY
WAKE-UP LOGIC
MSB
MSB
TxD BUFFER/SC0DRL
TxD BUFFER/SC0DRL
SC0SR1/INT STATUS
10-11 BIT SHIFT REG
10-11 BIT SHIFT REG
SC0CR2/SCI CTL 2
SC0CR2/SCI CTL 2
SCI TRANSMITTER
TxMTR CONTROL
SCI RECEIVER
LSB
LSB
MC68HC912B32TS/D
HC12B32 SCI BLOCK
MC68HC912B32
TxD
PS1
RxD
PS0

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