MC68HC912B32MFU8 MOTOROLA [Motorola, Inc], MC68HC912B32MFU8 Datasheet - Page 91

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MC68HC912B32MFU8

Manufacturer Part Number
MC68HC912B32MFU8
Description
16-Bit Microcontroller
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
MC68HC912B32
MC68HC912B32TS/D
SP0BR SPI BAUD RATE REGISTER
2
A clock phase control bit (CPHA) and a clock polarity control bit (CPOL) in the SP0CR1 register select
one of four possible clock formats to be used by the SPI system. The CPOL bit simply selects non-in-
verted or inverted clock. The CPHA bit is used to accommodate two fundamentally different protocols
by shifting the clock by one half cycle or no phase shift.
INTERRUPT
4
REQUEST
SPI
8
(SAME AS E RATE)
MCU P CLOCK
16
SELECT
DIVIDER
32
SP0SR SPI STATUS REGISTER
SPI CONTROL
64
Figure 21 Serial Peripheral Interface Block Diagram
128
256
SP0DR SPI DATA REGISTER
SHIFT CONTROL LOGIC
8-BIT SHIFT REGISTER
READ DATA BUFFER
INTERNAL BUS
MSTR
SPE
SP0CR1 SPI CONTROL REGISTER 1
CLOCK
LOGIC
CLOCK
SWOM
LSBF
SP0CR2 SPI CONTROL REGISTER 2
CONTROL
S
M
M
S
S
M
LOGIC
PIN
MOTOROLA
MISO
MOSI
SCK
PS7
PS4
PS5
PS6
SS
HC12 SPI BLOCK
91

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