MC68HC912B32MFU8 MOTOROLA [Motorola, Inc], MC68HC912B32MFU8 Datasheet - Page 94

• Manufacturer Part Number: MC68HC912B32MFU8
• Description: 16-Bit Microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

SPIE — SPI Interrupt Enable
SPE — SPI System Enable
SWOM — Port S Wired-OR Mode
MSTR — SPI Master/Slave Mode Select
CPOL, CPHA — SPI Clock Polarity, Clock Phase
SSOE — Slave Select Output Enable
LSBF — SPI LSB First Enable
SP0CR2 — SPI Control Register 2
SSWAI — SSI Stop in Wait Mode
SPC0 — Serial Pin Control 0
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MOTOROLA
RESET:
Read or write anytime.
When MODF is set, SPE always reads zero. SP0CR1 must be written as part of a mode fault recovery
sequence.
Controls not only SPI output pins but also the general-purpose output pins (PS[4:7]) which are not used
by SPI.
These two bits are used to specify the clock format to be used in SPI operations. When the clock polarity
bit is cleared and data is not being transferred, the SCK pin of the master device is low. When CPOL is
set, SCK idles high. See Figure 22 and Figure 23.
The SS output feature is enabled only in the master mode by asserting the SSOE and DDS7.
Normally data is transferred most significant bit first. This bit does not affect the position of the MSB and
LSB in the data register. Reads and writes of the data register will always have MSB in bit 7.
Read or write anytime.
This bit decides serial pin configurations with MSTR control bit.
1 = Hardware interrupt sequence is requested each time the SPIF or MODF status flag is set
0 = SPI interrupts are inhibited
0 = SPI internal hardware is initialized and SPI system is in a low-power disabled state.
1 = PS[4:7] are dedicated to the SPI function
0 = SPI and/or PS[4:7] output buffers operate normally
1 = SPI and/or PS[4:7] output buffers behave as open-drain outputs
0 = Slave mode
1 = Master mode
0 = Data is transferred most significant bit first
1 = Data is transferred least significant bit first
0 = SSI clock operate normally
1 = Halt SSI clock generation when in wait mode
Bit 7
0
0
6
0
0
5
0
0
4
0
0
3
0
0
2
0
0
SSWAI
1
0
MC68HC912B32TS/D
SPC0
Bit 0
MC68HC912B32
0
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