MC68HC912B32MFU8 MOTOROLA [Motorola, Inc], MC68HC912B32MFU8 Datasheet - Page 59

• Manufacturer Part Number: MC68HC912B32MFU8
• Description: 16-Bit Microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

RTIFLG — Real-Time Interrupt Flag Register
RTIF — Real-Time Interrupt Flag
COPCTL — COP Control Register
CME — Clock Monitor Enable
FCME — Force Clock Monitor Enable
FCM — Force Clock Monitor Reset
FCOP — Force COP Watchdog Reset
DISR — Disable Resets from COP Watchdog and Clock Monitor
CR2, CR1, CR0 — COP Watchdog Timer Rate Select Bits
MC68HC912B32
MC68HC912B32TS/D
RESET:
RESET:
RESET:
This bit is cleared automatically by a write to this register with this bit set.
Read and write anytime.
If FCME is set, this bit has no meaning nor effect.
Write once in normal modes, anytime in special modes. Read anytime.
In normal modes, when this bit is set, the clock monitor function cannot be disabled until a reset occurs.
In order to use both STOP and clock monitor, the CME bit should be cleared prior to executing a STOP
instruction and set after recovery from STOP. If you plan on using STOP always keep FCME = 0.
Writes are not allowed in normal modes, anytime in special modes. Read anytime.
If DISR is set, this bit has no effect.
Writes are not allowed in normal modes; can be written anytime in special modes. Read anytime.
If DISR is set, this bit has no effect.
Writes are not allowed in normal modes, anytime in special modes. Read anytime.
The COP system is driven by a constant frequency of E/2
but two stages of this divider to be bypassed for testing in special modes only.) These bits specify an
additional division factor to arrive at the COP time-out rate (the clock used for this module is the E clock).
Write once in normal modes, anytime in special modes. Read anytime.
0 = Time-out has not yet occurred.
1 = Set when the time-out period is met.
0 = Clock monitor is disabled. Slow clocks and stop instruction may be used.
1 = Slow or stopped clocks (including the stop instruction) will cause a clock reset sequence.
0 = Clock monitor follows the state of the CME bit.
1 = Slow or stopped clocks will cause a clock reset sequence.
0 = Normal operation.
1 = Force a clock monitor reset (if clock monitor is enabled).
0 = Normal operation.
1 = Force a COP reset (if COP is enabled).
0 = Normal operation.
1 = Regardless of other control bit states, COP and clock monitor will not generate a system reset.
RTIF
CME
Bit 7
Bit 7
0
0
0
FCME
6
0
0
6
0
0
FCM
5
0
0
5
0
0
FCOP
4
0
0
4
0
0
DISR
3
0
0
3
0
1
13
. (RTBYP in the RTICTL register allows all
CR2
2
0
0
2
0
0
CR1
1
0
0
1
0
0
Bit 0
Bit 0
CR0
0
0
1
1
MOTOROLA
Special
Normal
$0015
$0016
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