MC68HC912B32MFU8 MOTOROLA [Motorola, Inc], MC68HC912B32MFU8 Datasheet - Page 39

• Manufacturer Part Number: MC68HC912B32MFU8
• Description: 16-Bit Microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

STRE — Spare Test Row Enable
MWPR — Multiple Word Programming
FEECTL — Flash EEPROM Control Register
FEESWAI — Flash EEPROM Stop in Wait Control
SVFP — Status V
ERAS — Erase Control
LAT — Latch Control
MC68HC912B32
MC68HC912B32TS/D
RESET:
The spare test row consists of one Flash EEPROM array row. The reserved word at location 31 contains
production test information which must be maintained through several erase cycles. When STRE is set,
the decoding for the spare test row overrides the address lines which normally select the other rows in
the array.
Used primarily for testing, if MPWR = 1, the two least-significant address lines ADDR[1:0] will be ignored
when programming a Flash EEPROM location. The word location addressed if ADDR[1:0] = 00, along
with the word location addressed if ADDR[1:0] = 10, will both be programmed with the same word data
from the programming latches. This bit should not be changed during programming.
This register controls the programming and erasure of the Flash EEPROM.
SVFP is a read only bit.
This bit can be read anytime or written when ENPE = 0. When set, all locations in the array will be
erased at the same time. The boot block will be erased only if BOOTP = 0. This bit also affects the result
of attempted array reads. See Table 14 for more information. Status of ERAS cannot change if ENPE
is set.
This bit can be read anytime or written when ENPE = 0. When set, the Flash EEPROM is configured
for programming or erasure and, upon the next valid write to the array, the address and data will be
latched for the programming sequence. See Table 14 for the effects of LAT on array reads. A high volt-
age detect circuit on the V
at normal levels.
0 = LIB accesses are to the Flash EEPROM array
1 = Spare test row in array enabled if SMOD is active
0 = Multiple word programming disabled
1 = Program 32 bits of data
0 = Do not halt Flash EEPROM clock when the part is in wait mode.
1 = Halt Flash EEPROM clock when the part is in wait mode.
0 = Voltage of V
1 = Voltage of V
0 = Flash EEPROM configured for programming
1 = Flash EEPROM configured for erasure
0 = Programming latches disabled
1 = Programming latches enabled
Bit 7
0
0
The FEESWAI bit cannot be asserted if the interrupt vector resides in theFlash
EEPROM array.
FP
Voltage
FP
FP
6
0
0
pin is below normal programming voltage levels
pin is above normal programming voltage levels
FP
pin will prevent assertion of the LAT bit when the programming voltage is
5
0
0
FEESWAI
4
0
NOTE
SVFP
3
0
ERAS
2
0
LAT
1
0
ENPE
Bit 0
0
MOTOROLA
$00F7
39