MC68HC912B32MFU8 MOTOROLA [Motorola, Inc], MC68HC912B32MFU8 Datasheet - Page 7

• Manufacturer Part Number: MC68HC912B32MFU8
• Description: 16-Bit Microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

2.2 Data Types
2.3 Addressing Modes
MC68HC912B32
MC68HC912B32TS/D
(auto pre-decrement)
(auto post-increment)
(auto pre-increment)
(accumulator offset)
Addressing Mode
Indexed-Indirect
Indexed-Indirect
(D accumulator
The CPU12 supports the following data types:
A byte is eight bits wide and can be accessed at any byte location. A word is composed of two consec-
utive bytes with the most significant byte at the lower value address. There are no special requirements
for alignment of instructions or operands.
Addressing modes determine how the CPU accesses memory locations to be operated upon. The
CPU12 includes all of the addressing modes of the M68HC11 CPU as well as several new forms of in-
dexed addressing. Table 2 is a summary of the available addressing modes.
(16-bit offset)
(16-bit offset)
(5-bit offset)
(9-bit offset)
decrement)
Immediate
(auto post-
Extended
Inherent
Relative
Indexed
Indexed
Indexed
Indexed
Indexed
Indexed
Indexed
Indexed
offset)
Direct
• Bit data
• 8-bit and 16-bit signed and unsigned integers
• 16-bit unsigned fractions
• 16-bit addresses
(no externally supplied
INST [ oprx16 , xysp ]
INST oprx16 , xysp
INST oprx5 , xysp
INST oprx3 , –xys
INST oprx3,+xys
INST oprx3 , xys–
INST oprx3 , xys+
INST oprx9 , xysp
Source Format
INST abd , xysp
INST [D, xysp ]
INST # opr16i
INST opr16a
INST # opr8i
INST opr8a
INST rel16
operands)
Table 2 M68HC12 Addressing Mode Summary
INST rel8
INST
or
or
Abbreviation
[D,IDX]
[IDX2]
IDX1
IDX2
IMM
EXT
REL
INH
DIR
IDX
IDX
IDX
IDX
IDX
IDX
Indexed with 8-bit (A or B) or 16-bit (D) accumu-
Operand is the lower 8-bits of an address in the
An 8-bit or 16-bit relative offset from the current
5-bit signed constant offset from x, y, sp, or pc
9-bit signed constant offset from x, y, sp, or pc
(lower 8-bits of offset in one extension byte)
Operand is included in instruction stream
Auto post-decrement x, y, or sp by 1 ~ 8
16-bit constant offset from x, y, sp, or pc
16-bit constant offset from x, y, sp, or pc
Auto post-increment x, y, or sp by 1 ~ 8
Auto pre-decrement x, y, or sp by 1 ~ 8
Operands (if any) are in CPU registers
Auto pre-increment x, y, or sp by 1 ~ 8
(16-bit offset in two extension bytes)
(16-bit offset in two extension bytes)
8- or 16-bit size implied by context
x, y, sp, or pc plus the value in D
Pointer to operand is found at...
Pointer to operand is found at...
pc is supplied in the instruction
lator offset from x, y, sp, or pc
Operand is a 16-bit address
range $0000 – $00FF
Description
MOTOROLA
7