MC68HC912B32MFU8 MOTOROLA [Motorola, Inc], MC68HC912B32MFU8 Datasheet - Page 98

• Manufacturer Part Number: MC68HC912B32MFU8
• Description: 16-Bit Microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

14 Byte Data Link Communications Module (BDLC)
14.1 Features
14.2 BDLC Operating Modes
98
MOTOROLA
The byte data link communications module (BDLC) provides access to an external serial communica-
tion multiplex bus, operating according to the SAE J1850 protocol.
Features of the BDLC module include the following:
The BDLC has five main modes of operation which interact with the power supplies, pins and the MCU.
Power Off is entered from the reset mode whenever the BDLC supply voltage V
imum value for guaranteed operation. In this mode, the pin input and output specifications are not guar-
anteed.
Reset is entered from the power off mode whenever the BDLC supply voltage V
imum specified value and an MCU reset source is asserted. To prevent the BDLC from entering an un-
known state, the internal MCU reset is asserted while powering up the BDLC. In reset mode, the internal
BDLC voltage references are operative, V
reset state and the internal BDLC system clock is running. Registers will assume their reset condition.
Outputs are held in their programmed reset state. Inputs and network activity are ignored.
Run is entered from the reset mode after all MCU reset sources are no longer asserted. It is entered
from the BDLC wait mode whenever activity is sensed on the J1850 bus. Run mode is entered from the
BDLC stop mode whenever network activity is sensed though messages will not be received properly
until the clocks have stabilized and the CPU is also in the run mode. In run mode, normal network op-
eration takes place. Ensure that all BDLC transmissions cease before exiting this mode.
BDLC Wait power-conserving mode is automatically entered from the run mode whenever the CPU ex-
ecutes a WAIT instruction and if the WCM bit in the BCR register has been cleared. In this mode, the
BDLC internal clocks continue to run. The first passive-to-active transition of the bus wakes up the
BDLC and the CPU. If a valid byte is successfully received a CPU interrupt request will be generated.
BDLC Stop power-conserving mode is automatically entered from the run mode whenever the CPU
executes a STOP instruction, or if the CPU executes a WAIT instruction and the WCM bit in the BCR
register has been set. In this mode, the BDLC internal clocks are stopped until network activity is sensed
and a CPU interrupt request is generated.
• SAE J1850 compatible
• 10.4 Kbps VPW bit format
• Digital noise filter
• Collision detection
• Hardware CRC generation and checking
• Two power saving modes with automatic wake up on network activity
• Polling and CPU interrupts with vector lookup available
• Receive and transmit block mode supported
• Supports 4X receive mode (41.6 Kbps)
• Digital loopback mode
• In-frame response (IFR) types 0, 1, 2, and 3 supported
• Dedicated register for symbol timing adjustments
• Digital module only, requires external analog transceiver
It is recommended that the reader be familiar with the SAE Standard J1850 Class
B Data Communication Network Interface specification prior to proceeding with this
section.
DD
is supplied to the internal circuits, which are held in their
NOTE
DD
DD
MC68HC912B32TS/D
drops below the min-
rises above its min-
MC68HC912B32