LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 166

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
10.13 Receive filter register definitions
UM10360
User manual
10.13.1 Receive Filter Control Register (RxFilterCtrl - 0x5000 0200)
10.13.2 Receive Filter WoL Status Register (RxFilterWoLStatus - 0x5000 0204)
The Receive Filter Control register (RxFilterCtrl) has an address of 0x5000 0200.
Table 165
Table 165. Receive Filter Control register (RxFilterCtrl - address 0x5000 0200) bit description
The Receive Filter Wake-up on LAN Status register (RxFilterWoLStatus) is a read-only
register with an address of 0x5000 0204.
Table 166
Table 166. Receive Filter WoL Status register (RxFilterWoLStatus - address 0x5000 0204) bit
Bit
0
1
2
3
4
5
11:6
12
13
31:14 -
Bit
0
1
2
3
4
5
Symbol
AcceptUnicastWoL
AcceptBroadcastWoL
AcceptMulticastWoL
AcceptUnicastHashWoL
AcceptMulticastHashWoL When the value is ’1’, a multicast frame that passes the
AcceptPerfectWoL
Symbol
AcceptUnicastEn
AcceptBroadcastEn
AcceptMulticastEn
AcceptUnicastHashEn
AcceptMulticastHashEn
AcceptPerfectEn
-
MagicPacketEnWoL
RxFilterEnWoL
lists the definition of the individual bits in the register.
lists the definition of the individual bits in the register.
description
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Function
When the value is ’1’, a unicast frames caused WoL.
When the value is ’1’, a broadcast frame caused WoL.
When the value is ’1’, a multicast frame caused WoL.
When the value is ’1’, a unicast frame that passes the
imperfect hash filter caused WoL.
imperfect hash filter caused WoL.
When the value is ’1’, the perfect address matching filter
caused WoL.
Function
When set to ’1’, all unicast frames are accepted.
When set to ’1’, all broadcast frames are accepted.
When set to ’1’, all multicast frames are accepted.
When set to ’1’, unicast frames that pass the imperfect
hash filter are accepted.
When set to ’1’, multicast frames that pass the
imperfect hash filter are accepted.
When set to ’1’, the frames with a destination address
identical to the
station address are accepted.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
When set to ’1’, the result of the magic packet filter will
generate a WoL interrupt when there is a match.
When set to ’1’, the result of the perfect address
matching filter and the imperfect hash filter will
generate a WoL interrupt when there is a match.
Unused
Chapter 10: LPC17xx Ethernet
UM10360
© NXP B.V. 2010. All rights reserved.
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0
0
0
Reset
value
0
0
0
0
NA
0
0
0x0
Reset
value
0
0
0
0
0