LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 395

IC ARM CORTEX MCU 512K 80-LQFP

LPC1759FBD80,551

Manufacturer Part Number
LPC1759FBD80,551
Description
IC ARM CORTEX MCU 512K 80-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr

Specifications of LPC1759FBD80,551

Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
80-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
52
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 6x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
52
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 6 Channel
On-chip Dac
10 bit
Package
80LQFP
Device Core
ARM Cortex M3
Family Name
LPC17xx
Maximum Speed
120 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4968
935290523551

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NXP Semiconductors
UM10360
User manual
Fig 71. Detailed example of acceptance filter tables and ID index values
16.17.6 Configuration example 6
APB base +
100d = 64h
104d = 68h
124d = 7Ch
112d = 70h
116d = 74h
120d = 78h
92d = 5Ch
44d = 2Ch
48d = 30h
84d = 54h
88d = 58h
00d = 00h
04d = 04h
52d = 34h
address
SFF_GRP_sa 52 d := 034 h := 0 0011 0100 b
EFF_GRP_sa 112 d := 070 h := 0 0111 0000 b
EFF_sa
ENDofTable
SFF_sa
The Table below shows which sections and therefore which types of CAN identifiers are
used and activated. The ID-Look-up Table configuration of this example is shown in
Figure
000 d := 000 h := 0 0000 0000 b
100 d := 064 h := 0 0110 0100 b
128 d := 080 h := 0 1000 0000 b
72.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
lower_boundary
upper_boundary
lower_boundary
upper_boundary
lower_boundary 3 4 upper_boundary
lower_boundary 3
lower_boundary 3
column_lower
22
24
0
2
look-up table RAM
38
39
2 6
41
42
5 upper_boundary
6 upper_boundary
column_upper
23
25
1
3
Chapter 16: LPC17xx CAN1/2
ID index #
0
1
22
23
24
25
26 d
34 d
35 d
36 d
38 d
39 d
41 d
42 d
2
3
UM10360
© NXP B.V. 2010. All rights reserved.
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