LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 829

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
19.8.5
19.8.5.1
19.8.5.2
19.8.6
19.8.7
19.8.8
19.8.9
19.8.10
19.8.11
19.9
19.9.1
19.9.2
19.9.3
19.9.4
19.9.5
19.9.6
19.9.6.1
19.9.6.2
19.9.7
19.9.7.1
19.9.7.2
19.9.7.3
Chapter 20: LPC17xx I2S
20.1
20.2
UM10360
User manual
Details of I
Basic configuration . . . . . . . . . . . . . . . . . . . . 473
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
I
I
I2C1MMCTRL- 0x4005 C01C; I
I2C2MMCTRL- 0x400A 001C) . . . . . . . . . . . 444
Interrupt in Monitor mode . . . . . . . . . . . . . . . 445
Loss of arbitration in Monitor mode . . . . . . . 445
I
I2CDATA_BUFFER - 0x4001 C02C; I
I2C1DATA_BUFFER- 0x4005 C02C; I
I2C2DATA_BUFFER- 0x400A 002C) . . . . . . 446
I
I2C0ADR[0, 1, 2, 3]- 0x4001 C0[0C, 20, 24, 28];
I
0x4005 C0[0C, 20, 24, 28]; I
3] - address 0x400A 00[0C, 20, 24, 28]). . . . 446
I
I2C0MASK[0, 1, 2, 3] - 0x4001 C0[30, 34, 38, 3C];
I
0x4005 C0[30, 34, 38, 3C]; I
2, 3] - address 0x400A 00[30, 34, 38, 3C]). . 447
I
I2C0SCLH - 0x4001 C010; I
0x4005 C010; I
0010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
I
I2C0SCLL: 0x4001 C014; I
0x4005 C014; I
0014) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
Selecting the appropriate I
cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
Master Transmitter mode . . . . . . . . . . . . . . . 450
Master Receiver mode . . . . . . . . . . . . . . . . . 452
Slave Receiver mode . . . . . . . . . . . . . . . . . . 454
Slave Transmitter mode . . . . . . . . . . . . . . . . 456
Detailed state tables . . . . . . . . . . . . . . . . . . . 457
Miscellaneous states . . . . . . . . . . . . . . . . . . 462
I2STAT = 0xF8 . . . . . . . . . . . . . . . . . . . . . . . 462
I2STAT = 0x00 . . . . . . . . . . . . . . . . . . . . . . . 462
Some special cases . . . . . . . . . . . . . . . . . . . 462
Simultaneous repeated START conditions from
two masters . . . . . . . . . . . . . . . . . . . . . . . . . 462
Data transfer after loss of arbitration . . . . . . 463
Forced access to the I
2
2
2
2
2
2
2
2
2
C Monitor mode control register (I2MMCTRL:
C0, I2C0MMCTRL - 0x4001 C01C; I
C Data buffer register (I2DATA_BUFFER: I
C Slave Address registers (I2ADR0 to 3: I
C1, I2C1ADR[0, 1, 2, 3] - address
C Mask registers (I2MASK0 to 3: I
C1, I2C1MASK[0, 1, 2, 3] - address
C SCL HIGH duty cycle register (I2SCLH: I
C SCL Low duty cycle register (I2SCLL: I
2
C operating modes. . . . . . . . . . . 449
2
2
C2, I2C2SCLH - 0x400A
C2 - I2C2SCLL: 0x400A
2
C-bus . . . . . . . . . . . . 463
2
2
C data rate and duty
2
2
C1 - I2C1SCLL:
2
C2, I2C2ADR[0, 1, 2,
C2, I2C2MASK[0, 1,
C1, I2C1SCLH -
2
All information provided in this document is subject to legal disclaimers.
C2,
2
C0,
2
2
2
C1,
C1,
C2,
Rev. 2 — 19 August 2010
2
2
C0 -
2
C0,
2
C0,
C0,
19.9.7.4
19.9.7.5
19.9.8
19.9.8.1
19.9.8.2
19.9.8.3
19.9.8.4
19.10
19.10.1
19.10.2
19.10.3
19.10.4
19.10.5
19.10.5.1 State: 0x00 . . . . . . . . . . . . . . . . . . . . . . . . . . 466
19.10.5.2 Master States . . . . . . . . . . . . . . . . . . . . . . . . 467
19.10.5.3 State: 0x08 . . . . . . . . . . . . . . . . . . . . . . . . . . 467
19.10.5.4 State: 0x10 . . . . . . . . . . . . . . . . . . . . . . . . . . 467
19.10.6
19.10.6.1 State: 0x18 . . . . . . . . . . . . . . . . . . . . . . . . . . 467
19.10.6.2 State: 0x20 . . . . . . . . . . . . . . . . . . . . . . . . . . 468
19.10.6.3 State: 0x28 . . . . . . . . . . . . . . . . . . . . . . . . . . 468
19.10.6.4 State: 0x30 . . . . . . . . . . . . . . . . . . . . . . . . . . 468
19.10.6.5 State: 0x38 . . . . . . . . . . . . . . . . . . . . . . . . . . 468
19.10.7
19.10.7.1 State: 0x40 . . . . . . . . . . . . . . . . . . . . . . . . . . 468
19.10.7.2 State: 0x48 . . . . . . . . . . . . . . . . . . . . . . . . . . 469
19.10.7.3 State: 0x50 . . . . . . . . . . . . . . . . . . . . . . . . . . 469
19.10.7.4 State: 0x58 . . . . . . . . . . . . . . . . . . . . . . . . . . 469
19.10.8
19.10.8.1 State: 0x60 . . . . . . . . . . . . . . . . . . . . . . . . . . 469
19.10.8.2 State: 0x68 . . . . . . . . . . . . . . . . . . . . . . . . . . 470
19.10.8.3 State: 0x70 . . . . . . . . . . . . . . . . . . . . . . . . . . 470
19.10.8.4 State: 0x78 . . . . . . . . . . . . . . . . . . . . . . . . . . 470
19.10.8.5 State: 0x80 . . . . . . . . . . . . . . . . . . . . . . . . . . 470
19.10.8.6 State: 0x88 . . . . . . . . . . . . . . . . . . . . . . . . . . 471
19.10.8.7 State: 0x90 . . . . . . . . . . . . . . . . . . . . . . . . . . 471
19.10.8.8 State: 0x98 . . . . . . . . . . . . . . . . . . . . . . . . . . 471
19.10.8.9 State: 0xA0. . . . . . . . . . . . . . . . . . . . . . . . . . 471
19.10.9
19.10.9.1 State: 0xA8. . . . . . . . . . . . . . . . . . . . . . . . . . 471
19.10.9.2 State: 0xB0. . . . . . . . . . . . . . . . . . . . . . . . . . 472
19.10.9.3 State: 0xB8. . . . . . . . . . . . . . . . . . . . . . . . . . 472
19.10.9.4 State: 0xC0 . . . . . . . . . . . . . . . . . . . . . . . . . 472
19.10.9.5 State: 0xC8 . . . . . . . . . . . . . . . . . . . . . . . . . 472
20.3
20.4
Software example . . . . . . . . . . . . . . . . . . . . . 466
Description . . . . . . . . . . . . . . . . . . . . . . . . . . 474
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . 475
I
SDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
Bus error . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
I
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 465
I
The state service routines . . . . . . . . . . . . . . 465
Adapting state services to an application. . . 465
Initialization routine . . . . . . . . . . . . . . . . . . . 466
Start Master Transmit function . . . . . . . . . . . 466
Start Master Receive function . . . . . . . . . . . 466
I
Non mode specific states. . . . . . . . . . . . . . . 466
Master Transmitter states . . . . . . . . . . . . . . 467
Master Receive states . . . . . . . . . . . . . . . . . 468
Slave Receiver states . . . . . . . . . . . . . . . . . 469
Slave Transmitter states . . . . . . . . . . . . . . . 471
2
2
2
2
C-bus obstructed by a LOW level on SCL or
C state service routines . . . . . . . . . . . . . . . 465
C interrupt service . . . . . . . . . . . . . . . . . . . 465
C interrupt routine . . . . . . . . . . . . . . . . . . . 466
Chapter 35: Supplementary information
UM10360
© NXP B.V. 2010. All rights reserved.
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