LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 264
LPC1759FBD80,551
Manufacturer Part Number
LPC1759FBD80,551
Description
IC ARM CORTEX MCU 512K 80-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1751FBD80551.pdf
(74 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
Specifications of LPC1759FBD80,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
80-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
52
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 6x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
52
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 6 Channel
On-chip Dac
10 bit
Package
80LQFP
Device Core
ARM Cortex M3
Family Name
LPC17xx
Maximum Speed
120 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4968
935290523551
935290523551
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UM10360
User manual
Fig 32. Data transfer in ATLE mode
data to be sent
by host driver
160 bytes
100 bytes
Figure 32
two USB transfers of 160 bytes and 100 bytes, respectively. Given a MaxPacketSize of
64, the device hardware interprets this USB transfer as four packets of 64 bytes and a
short packet of 4 bytes. The third and fourth packets are concatenated. Note that in
Normal mode, the USB transfer would be interpreted as packets of 64, 64, 32, and 64 and
36 bytes.
It is now the responsibility of the DMA engine to separate these two USB transfers and put
them in the memory locations in the DMA_buffer_start_addr field of DMA Descriptor 1
(DD1) and DMA Descriptor 2 (DD2).
Hardware reads the two-byte-wide DMA_buffer_length at the offset (from the start of the
USB transfer) specified by Message_length_position from the incoming data packets and
writes it in the DMA_buffer_length field of the DD. To ensure that both bytes of the
DMA_buffer_length are extracted in the event they are split between two packets, the
flags LS_byte_extracted and MS_byte_extracted are set by hardware after the respective
byte is extracted. After the extraction of the MS byte, the DMA transfer continues as in the
normal mode.
The flags LS_byte_extracted and MS_byte_extracted are set to 0 by software when
preparing a new DD. Therefore, once a DD is retired, the transfer length is extracted again
for the next DD.
If DD1 is retired during the transfer of a concatenated packet (such as the third packet in
Figure
retired with DD_status set to the DataOverrun status code. This is treated as an error
condition and the corresponding EPxx_DMA_ENABLE bit of USBEpDMASt is cleared by
hardware.
32), and DD2 is not programmed (Next_DD_valid field of DD1 is 0), then DD1 is
shows a typical OUT USB transfer in ATLE mode, where the host concatenates
as seen on USB
data in packets
All information provided in this document is subject to legal disclaimers.
4 bytes
64 bytes
64 bytes
32 bytes
32 bytes
64 bytes
Rev. 2 — 19 August 2010
data to be stored in
RAM by DMA engine
Chapter 11: LPC17xx USB device controller
160 bytes
100 bytes
DMA_buffer_start_addr
of DD1
DMA_buffer_start_addr
of DD2
UM10360
© NXP B.V. 2010. All rights reserved.
264 of 840
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