LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 344

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
16.4 Pin description
16.5 CAN controller architecture
UM10360
User manual
16.3.2 CAN controller features
16.3.3 Acceptance filter features
Table 311. CAN Pin descriptions
The CAN Controller is a complete serial interface with both Transmit and Receive Buffers
but without Acceptance Filter. CAN Identifier filtering is done for all CAN channels in a
separate block (Acceptance Filter). Except for message buffering and acceptance filtering
the functionality is similar to the PeliCAN concept.
The CAN Controller Block includes interfaces to the following blocks:
Pin Name
RD1, RD2
TD1, TD2
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Guaranteed latency time for high priority messages.
Programmable transfer rate (up to 1 Mbit/s).
Multicast and broadcast message facility.
Data length from 0 up to 8 bytes.
Powerful error handling capability.
Non-return-to-zero (NRZ) encoding/decoding with bit stuffing.
2 CAN controllers and buses.
Supports 11-bit identifier as well as 29-bit identifier.
Double Receive Buffer and Triple Transmit Buffer.
Programmable Error Warning Limit and Error Counters with read/write access.
Arbitration Lost Capture and Error Code Capture with detailed bit position.
Single Shot Transmission (no re-transmission).
Listen Only Mode (no acknowledge, no active error flags).
Reception of "own" messages (Self Reception Request).
Fast hardware implemented search algorithm supporting a large number of CAN
identifiers.
Global Acceptance Filter recognizes 11-bit and 29-bit Rx Identifiers for all CAN buses.
Allows definition of explicit and groups for 11-bit and 29-bit CAN identifiers.
Acceptance Filter can provide FullCAN-style automatic reception for selected
Standard Identifiers.
APB Interface
Acceptance Filter
Type
Input
Output
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Description
Serial Inputs. From CAN transceivers.
Serial Outputs. To CAN transceivers.
Chapter 16: LPC17xx CAN1/2
UM10360
© NXP B.V. 2010. All rights reserved.
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