LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 70

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
5.4 Flash Accelerator Configuration register (FLASHCFG - 0x400F C000)
Table 49.
5.5 Operation
UM10360
User manual
Bit
11:0
15:12 FLASHTIM
31:16 -
Symbol
-
Flash Accelerator Configuration register (FLASHCFG - address 0x400F C000) bit description
Value Description
-
0000
0001
0010
0011
0100
0101
Other Intended for potential future higher speed devices.
Configuration bits select the flash access time, as shown in
FLASHCFG control internal flash accelerator functions and should not be altered.
Following reset, flash accelerator functions are enabled and flash access timing is set to a
default value of 4 clocks.
Changing the FLASHCFG register value causes the flash accelerator to invalidate all of
the holding latches, resulting in new reads of flash information as required. This
guarantees synchronization of the flash accelerator to CPU operation.
Simply put, the flash accelerator attempts to have the next Cortex-M3 instruction that will
be needed in its latches in time to prevent CPU fetch stalls. The LPC17xx uses one bank
of flash memory. The flash accelerator includes an array of eight 128-bit buffers to store
both instructions and data in a configurable manner. Each 128-bit buffer in the array can
include four 32-bit instructions, eight 16-bit instructions or some combination of the two.
During sequential code execution, a buffer typically contains the current instruction and
the entire flash line that contains that instruction, or one flash line of data containing a
previously requested address. Buffers are marked according to how they are used (as
instruction or data buffers), and when they have been accessed. This information is used
to carry out the buffer replacement strategy.
The Cortex-M3 provides a separate bus for instruction access (I-code) and data access
(D-code) in the code memory space. These buses, plus the General Purpose DMA
Controllers’s master port, are arbitrated by the AHB multilayer matrix. Any access to the
flash memory’s address space is presented to the flash accelerator.
Reserved, user software should not change these bits from the reset value.
Flash access time. The value of this field plus 1 gives the number of CPU clocks used
Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock.
Flash accesses use 3 CPU clocks. Use for up to 60 MHz CPU clock.
Flash accesses use 4 CPU clocks. Use for up to 80 MHz CPU clock.
Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock.
Use for up to 120 Mhz for LPC1759 and LPC1769 only.
Flash accesses use 6 CPU clocks. This “safe” setting will work under any conditions.
Reserved. The value read from a reserved bit is not defined.
for a flash access.
Warning: improper setting of this value may result in incorrect operation of the device.
Flash accesses use 1 CPU clock. Use for up to 20 MHz CPU clock.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 5: LPC17xx Flash accelerator
Table
49. The lower bits of
UM10360
© NXP B.V. 2010. All rights reserved.
70 of 840
Reset
value
0x03A
0x3
NA