LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 825
LPC1759FBD80,551
Manufacturer Part Number
LPC1759FBD80,551
Description
IC ARM CORTEX MCU 512K 80-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1751FBD80551.pdf
(74 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
Specifications of LPC1759FBD80,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
80-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
52
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 6x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
52
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 6 Channel
On-chip Dac
10 bit
Package
80LQFP
Device Core
ARM Cortex M3
Family Name
LPC17xx
Maximum Speed
120 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4968
935290523551
935290523551
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Quantity
Price
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NXP Semiconductors
14.4.6
14.4.6.1
14.4.7
14.4.8
14.4.9
14.4.10
Chapter 15: LPC17xx UART1
15.1
15.2
15.3
15.4
15.4.1
15.4.2
15.4.3
15.4.4
15.4.5
15.4.6
15.4.6.1
15.4.7
15.4.8
15.4.9
15.4.9.1
15.4.9.2
15.4.10
UM10360
User manual
Basic configuration . . . . . . . . . . . . . . . . . . . . 318
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 319
Register description . . . . . . . . . . . . . . . . . . . 320
UARTn FIFO Control Register (U0FCR -
0x4000 C008, U2FCR - 0x4009 8008, U3FCR -
0x4009 C008) . . . . . . . . . . . . . . . . . . . . . . . . 305
DMA Operation . . . . . . . . . . . . . . . . . . . . . . . 305
UART receiver DMA . . . . . . . . . . . . . . . . . . . .305
UART transmitter DMA . . . . . . . . . . . . . . . . . .306
UARTn Line Control Register (U0LCR -
0x4000 C00C, U2LCR - 0x4009 800C, U3LCR -
0x4009 C00C) . . . . . . . . . . . . . . . . . . . . . . . 306
UARTn Line Status Register (U0LSR -
0x4000 C014, U2LSR - 0x4009 8014, U3LSR -
0x4009 C014) . . . . . . . . . . . . . . . . . . . . . . . . 306
UARTn Scratch Pad Register (U0SCR -
0x4000 C01C, U2SCR - 0x4009 801C U3SCR -
0x4009 C01C) . . . . . . . . . . . . . . . . . . . . . . . 308
UARTn Auto-baud Control Register (U0ACR -
0x4000 C020, U2ACR - 0x4009 8020, U3ACR -
0x4009 C020) . . . . . . . . . . . . . . . . . . . . . . . . 308
UART1 Receiver Buffer Register (U1RBR -
0x4001 0000, when DLAB = 0). . . . . . . . . . . 321
UART1 Transmitter Holding Register (U1THR -
0x4001 0000 when DLAB = 0) . . . . . . . . . . . 321
UART1 Divisor Latch LSB and MSB Registers
(U1DLL - 0x4001 0000 and U1DLM -
0x4001 0004, when DLAB = 1). . . . . . . . . . . 321
UART1 Interrupt Enable Register (U1IER -
0x4001 0004, when DLAB = 0). . . . . . . . . . . 322
UART1 Interrupt Identification Register (U1IIR -
0x4001 0008) . . . . . . . . . . . . . . . . . . . . . . . . 323
UART1 FIFO Control Register (U1FCR -
0x4001 0008) . . . . . . . . . . . . . . . . . . . . . . . . 325
DMA Operation . . . . . . . . . . . . . . . . . . . . . . . 325
UART receiver DMA . . . . . . . . . . . . . . . . . . . .326
UART transmitter DMA . . . . . . . . . . . . . . . . . .326
UART1 Line Control Register (U1LCR -
0x4001 000C) . . . . . . . . . . . . . . . . . . . . . . . . 326
UART1 Modem Control Register (U1MCR -
0x4001 0010) . . . . . . . . . . . . . . . . . . . . . . . . 326
Auto-flow control . . . . . . . . . . . . . . . . . . . . . . 327
Auto-RTS . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Auto-CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
UART1 Line Status Register (U1LSR -
0x4001 0014) . . . . . . . . . . . . . . . . . . . . . . . . 329
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
14.4.10.1 Auto-baud . . . . . . . . . . . . . . . . . . . . . . . . . . 309
14.4.10.2 Auto-baud modes. . . . . . . . . . . . . . . . . . . . . 310
14.4.11
14.4.12
14.4.12.1 Baud rate calculation . . . . . . . . . . . . . . . . . . 313
14.4.12.1.1 Example 1: PCLK = 14.7456 MHz, BR =
14.4.12.1.2 Example 2: PCLK = 12 MHz, BR = 115200 315
14.4.13
14.5
15.4.11
15.4.12
15.4.13
15.4.14
15.4.15
15.4.16
15.4.16.1 Baud rate calculation . . . . . . . . . . . . . . . . . . 335
15.4.16.1.1 Example 1: PCLK = 14.7456 MHz, BR =
15.4.16.1.2 Example 2: PCLK = 12 MHz, BR = 115200 337
15.4.17
15.4.18
15.4.19
15.4.20
15.4.21
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 316
UARTn IrDA Control Register (U0ICR - 0x4000
C024, U2ICR - 0x4009 8024, U3ICR -
0x4009 C024) . . . . . . . . . . . . . . . . . . . . . . . . 311
UARTn Fractional Divider Register (U0FDR -
0x4000 C028, U2FDR - 0x4009 8028, U3FDR -
0x4009 C028) . . . . . . . . . . . . . . . . . . . . . . . 312
9600 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
UARTn Transmit Enable Register (U0TER -
0x4000 C030, U2TER - 0x4009 8030, U3TER -
0x4009 C030) . . . . . . . . . . . . . . . . . . . . . . . 315
UART1 Modem Status Register (U1MSR -
0x4001 0018) . . . . . . . . . . . . . . . . . . . . . . . . 330
UART1 Scratch Pad Register (U1SCR -
0x4001 001C) . . . . . . . . . . . . . . . . . . . . . . . 331
UART1 Auto-baud Control Register (U1ACR -
0x4001 0020) . . . . . . . . . . . . . . . . . . . . . . . . 331
Auto-baud . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Auto-baud modes. . . . . . . . . . . . . . . . . . . . . 333
UART1 Fractional Divider Register (U1FDR -
0x4001 0028) . . . . . . . . . . . . . . . . . . . . . . . . 334
9600 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
UART1 Transmit Enable Register (U1TER -
0x4001 0030) . . . . . . . . . . . . . . . . . . . . . . . . 337
UART1 RS485 Control register (U1RS485CTRL -
0x4001 004C) . . . . . . . . . . . . . . . . . . . . . . . 338
UART1 RS-485 Address Match register
(U1RS485ADRMATCH - 0x4001 0050) . . . . 339
UART1 RS-485 Delay value register
(U1RS485DLY - 0x4001 0054) . . . . . . . . . . 339
RS-485/EIA-485 modes of operation . . . . . . 339
RS-485/EIA-485 Normal Multidrop Mode
(NMM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
RS-485/EIA-485 Auto Address Detection (AAD)
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
RS-485/EIA-485 Auto Direction Control. . . . . 340
RS485/EIA-485 driver delay time. . . . . . . . . . 340
RS485/EIA-485 output inversion . . . . . . . . . . 341
Chapter 35: Supplementary information
UM10360
© NXP B.V. 2010. All rights reserved.
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