LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 40

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
UM10360
User manual
4.5.10 PLL0 frequency calculation
4.5.7 PLL0 Modes
4.5.8 PLL0 Feed register (PLL0FEED - 0x400F C08C)
4.5.9 PLL0 and Power-down mode
The combinations of PLLE0 and PLLC0 are shown in
Table 23.
A correct feed sequence must be written to the PLL0FEED register in order for changes to
the PLL0CON and PLL0CFG registers to take effect. The feed sequence is:
The two writes must be in the correct sequence, and there must be no other register
access in the same address space (0x400F C000 to 0x400F FFFF) between them.
Because of this, it may be necessary to disable interrupts for the duration of the PLL0 feed
operation, if there is a possibility that an interrupt service routine could write to another
register in that space. If either of the feed values is incorrect, or one of the previously
mentioned conditions is not met, any changes to the PLL0CON or PLL0CFG register will
not become effective.
Table 24.
Power-down mode automatically turns off and disconnects PLL0. Wake-up from
Power-down mode does not automatically restore PLL0 settings, this must be done in
software. Typically, a routine to activate PLL0, wait for lock, and then connect PLL0 can be
called at the beginning of any interrupt service routine that might be called due to the
wake-up. It is important not to attempt to restart PLL0 by simply feeding it when execution
resumes after a wake-up from Power-down mode. This would enable and connect PLL0
at the same time, before PLL lock is established.
PLL0 equations use the following parameters:
PLLC0 PLLE0 PLL Function
0
0
1
1
Bit
7:0
31:8
1. Write the value 0xAA to PLL0FEED.
2. Write the value 0x55 to PLL0FEED.
Symbol
PLL0FEED The PLL0 feed sequence must be written to this register in order for
-
0
1
0
1
PLL control bit combinations
PLL Feed register (PLL0FEED - address 0x400F C08C) bit description
All information provided in this document is subject to legal disclaimers.
Same as 00 combination. This prevents the possibility of PLL0 being connected
PLL0 is turned off and disconnected. PLL0 outputs the unmodified clock input.
PLL0 is active, but not yet connected. PLL0 can be connected after PLOCK0 is
asserted.
without also being enabled.
PLL0 is active and has been connected as the system clock source.
Description
PLL0 configuration and control register changes to take effect.
value read from a reserved bit is not defined.
Reserved, user software should not write ones to reserved bits. The
Rev. 2 — 19 August 2010
Chapter 4: LPC17xx Clocking and power control
Table
23.
UM10360
© NXP B.V. 2010. All rights reserved.
40 of 840
Reset
value
0x00
NA