LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 292

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
UM10360
User manual
Fig 43. State transitions implemented in software during A-device switching from host to peripheral
no
bit in external OTG transceiver
clear BDIS_ACON_EN
discharge V
Note that only the subset of A-device HNP states and state transitions supported by
hardware are shown. Software is responsible for implementing all of the HNP states.
Figure 43
this is not necessary if the corresponding interrupt is enabled.
Following are code examples that show how the actions in
The examples assume that ISP1302 is being used as the external OTG transceiver.
Set BDIS_ACON_EN in external OTG transceiver
a_wait_vfall
TMR set?
go to
yes
BUS
may appear to imply that the interrupt bits such as TMR should be polled, but
All information provided in this document is subject to legal disclaimers.
when host sends SET_FEATURE
no
in external OTG transceiver
load and enable OTG timer
Rev. 2 — 19 August 2010
suspend host on port 1
set BDIS_ACON_EN
HNP_SUCCESS set?
with a_hnp_enable,
set A_HNP_TRACK
stop the OTG timer
a_peripheral
a_suspend
a_host
go to
go to
yes
bit in external OTG transceiver
clear BDIS_ACON_EN
HNP_FAILURE set?
stop OTG timer
Chapter 13: LPC17xx USB OTG
a_host
go to
Figure 43
yes
are accomplished.
UM10360
no
© NXP B.V. 2010. All rights reserved.
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