LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 251

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
Table 249. Set Endpoint Status command bit description
UM10360
User manual
Bit
0
4:1
5
6
7
Symbol
ST
-
DA
RF_MO
CND_ST
11.12.12 Set Endpoint Status (Command: 0x40 - 0x55, Data: write 1 byte
11.12.13 Clear Buffer (Command: 0xF2, Data: read 1 byte (optional))
Value
0
1
-
0
1
0
1
0
1
Remark: This command may be invoked by using the USBCmdCode and USBCmdData
registers, or by setting the corresponding bit in USBEpIntClr. For ease of use, using the
USBEpIntClr register is recommended.
(optional))
The Set Endpoint Status command sets status bits 7:5 and 0 of the endpoint. The
Command Code of Set Endpoint Status is equal to the sum of 0x40 and the physical
endpoint number in hex. Not all bits can be set for all types of endpoints.
When an OUT packet sent by the host has been received successfully, an internal
hardware FIFO status Buffer_Full flag is set. All subsequent packets will be refused by
returning a NAK. When the device software has read the data, it should free the buffer by
issuing the Clear Buffer command. This clears the internal Buffer_Full flag. When the
buffer is cleared, new packets will be accepted.
When bit 0 of the optional data byte is 1, the previously received packet was over-written
by a SETUP packet. The Packet over-written bit is used only in control transfers.
According to the USB specification, a SETUP packet should be accepted irrespective of
the buffer status. The software should always check the status of the PO bit after reading
Description
Stalled endpoint bit. A Stalled control endpoint is automatically unstalled when it
receives a SETUP token, regardless of the content of the packet. If the endpoint
should stay in its stalled state, the CPU can stall it again by setting this bit. When
a stalled endpoint is unstalled - either by the Set Endpoint Status command or by
receiving a SETUP token - it is also re-initialized. This flushes the buffer: in case
of an OUT buffer it waits for a DATA 0 PID; in case of an IN buffer it writes a DATA
0 PID. There is no change of the interrupt status of the endpoint. When already
unstalled, writing a zero to this bit initializes the endpoint. When an endpoint is
stalled by the Set Endpoint Status command, it is also re-initialized.
The endpoint is unstalled.
The endpoint is stalled.
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
Disabled endpoint bit.
The endpoint is enabled.
The endpoint is disabled.
Rate Feedback Mode.
Interrupt endpoint is in the Toggle mode.
Interrupt endpoint is in the Rate Feedback mode. This means that transfer takes
place without data toggle bit.
Conditional Stall bit.
Unstalls both control endpoints.
Stall both control endpoints, unless the STP bit is set in the Select Endpoint
register. It is defined only for control OUT endpoints.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 11: LPC17xx USB device controller
UM10360
© NXP B.V. 2010. All rights reserved.
0
0
0
Reset value
0
NA
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