LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 610

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
UM10360
User manual
31.6.2.3 Memory-to-memory DMA flow
31.6.3 Interrupt requests
For a memory-to-memory DMA flow the following sequence occurs:
Note: Memory-to-memory transfers should be programmed with a low channel priority,
otherwise other DMA channels cannot access the bus until the memory-to-memory
transfer has finished, or other AHB masters cannot perform any transaction.
Interrupt requests can be generated when an AHB error is encountered or at the end of a
transfer (terminal count), after all the data corresponding to the current LLI has been
transferred to the destination. The interrupts can be masked by programming bits in the
relevant DMACCxControl and DMACCxConfig Channel Registers. The interrupt requests
from all DMA channels can be found in the DMACRawIntTCStat and DMACRawIntErrStat
registers. The masked versions of the DMA interrupt data is contained in the
DMACIntTCStat and DMACIntErrStat registers. The DMACIntStat register then combines
the DMACIntTCStat and DMACIntErrStat requests into a single register to enable the
source of an interrupt to be found quickly. Writing to the DMACIntTCClear or the
DMACIntErrClr Registers with a bit set to 1 enables selective clearing of interrupts.
7. When the destination DMA request goes active and there is data in the DMA
8. If an error occurs while transferring the data, an error interrupt is generated, the DMA
9. If the transfer has completed it is indicated by the transfer count reaching 0. The
1. Program and enable the DMA channel.
2. Transfer data whenever the DMA channel has the highest pending priority and the
3. If an error occurs while transferring the data, generate an error interrupt and disable
4. Decrement the transfer count.
5. If the count has reached zero:
Controller FIFO, transfer data into the destination peripheral.
stream is disabled, and the flow sequence ends.
following happens:
– The DMA Controller responds with a DMA acknowledge to the destination
– The terminal count interrupt is generated (this interrupt can be masked).
– If the DMACCxLLI Register is not 0, then reload the DMACCxSrcAddr,
DMA Controller gains mastership of the AHB bus.
the DMA stream.
– Generate a terminal count interrupt (the interrupt can be masked).
– If the DMACCxLLI Register is not 0, then reload the DMACCxSrcAddr,
peripheral.
DMACCxDestAddr, DMACCxLLI, and DMACCxControl Registers and go to back
to step 2. However, if DMACCxLLI is 0, the DMA stream is disabled and the flow
sequence ends.
DMACCxDestAddr, DMACCxLLI, and DMACCxControl Registers and go to back
to step 2. However, if DMACCxLLI is 0, the DMA stream is disabled and the flow
sequence ends.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 31: LPC17xx General Purpose DMA (GPDMA)
UM10360
© NXP B.V. 2010. All rights reserved.
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