LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 339

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
Table 308: UART1 RS485 Control register (U1RS485CTRL - address 0x4001 004C) bit description
Table 309. UART1 RS-485 Address Match register (U1RS485ADRMATCH - address 0x4001 0050) bit description
Table 310. UART1 RS-485 Delay value register (U1RS485DLY - address 0x4001 0054) bit description
UM10360
User manual
Bit
5
31:6
Bit
7:0
31:8
Bit
7:0
31:8
Symbol
ADRMATCH
-
Symbol
DLY
-
Symbol
OINV
-
15.4.19 UART1 RS-485 Address Match register (U1RS485ADRMATCH -
15.4.20 UART1 RS-485 Delay value register (U1RS485DLY - 0x4001 0054)
15.4.21 RS-485/EIA-485 modes of operation
Value Description
0
1
-
Description
Contains the address match value.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Description
Contains the direction control (RTS or DTR) delay value. This register works in
conjunction with an 8-bit counter.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
0x4001 0050)
The U1RS485ADRMATCH register contains the address match value for RS-485/EIA-485
mode.
The user may program the 8-bit RS485DLY register with a delay between the last stop bit
leaving the TXFIFO and the de-assertion of RTS (or DTR). This delay time is in periods of
the baud clock. Any delay time from 0 to 255 bit times may be programmed.
The RS-485/EIA-485 feature allows the UART to be configured as an addressable slave.
The addressable slave is one of multiple slaves controlled by a single master.
The UART master transmitter will identify an address character by setting the parity (9th)
bit to ‘1’. For data characters, the parity bit is set to ‘0’.
Each UART slave receiver can be assigned a unique address. The slave can be
programmed to either manually or automatically reject data following an address which is
not theirs.
RS-485/EIA-485 Normal Multidrop Mode (NMM)
Setting the RS485CTRL bit 0 enables this mode. In this mode, an address is detected
when a received byte causes the UART to set the parity error and generate an interrupt.
This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin. 0
The direction control pin will be driven to logic ‘0’ when the transmitter has data to
be sent. It will be driven to logic ‘1’ after the last bit of data has been transmitted.
The direction control pin will be driven to logic ‘1’ when the transmitter has data to
be sent. It will be driven to logic ‘0’ after the last bit of data has been transmitted.
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 15: LPC17xx UART1
UM10360
© NXP B.V. 2010. All rights reserved.
Reset value
NA
0x00
Reset value
NA
Reset value
0x00
NA
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