LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 407

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
UM10360
User manual
Table 361: SPI Control Register (S0SPCR - address 0x4002 0000) bit description
Bit
1:0
2
3
4
5
6
7
11:8
31:12 -
Symbol
-
BitEnable
CPHA
CPOL
MSTR
LSBF
SPIE
BITS
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
0
1
0
1
0
1
0
1
0
1
1000
1001
1010
1011
1100
1101
1110
1111
0000
Rev. 2 — 19 August 2010
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
The SPI controller sends and receives 8 bits of data per
transfer.
The SPI controller sends and receives the number of bits
selected by bits 11:8.
Clock phase control determines the relationship between the
data and the clock on SPI transfers, and controls when a slave
transfer is defined as starting and ending.
Data is sampled on the first clock edge of SCK. A transfer starts
and ends with activation and deactivation of the SSEL signal.
Data is sampled on the second clock edge of the SCK. A
transfer starts with the first clock edge, and ends with the last
sampling edge when the SSEL signal is active.
Clock polarity control.
SCK is active high.
SCK is active low.
Master mode select.
The SPI operates in Slave mode.
The SPI operates in Master mode.
LSB First controls which direction each byte is shifted when
transferred.
SPI data is transferred MSB (bit 7) first.
SPI data is transferred LSB (bit 0) first.
Serial peripheral interrupt enable.
SPI interrupts are inhibited.
A hardware interrupt is generated each time the SPIF or MODF
bits are activated.
When bit 2 of this register is 1, this field controls the number of
bits per transfer:
8 bits per transfer
9 bits per transfer
10 bits per transfer
11 bits per transfer
12 bits per transfer
13 bits per transfer
14 bits per transfer
15 bits per transfer
16 bits per transfer
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Chapter 17: LPC17xx SPI
UM10360
© NXP B.V. 2010. All rights reserved.
407 of 840
Reset
Value
NA
0
0
0
0
0
0
0000
NA