LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 679

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
UM10360
User manual
34.2.5.1.4 Condition flags
34.2.5.1.5 Examples
34.2.5.1.6 Multiword arithmetic examples
Note
When Rd is PC in the cond instruction:
If S is specified, these instructions update the N, Z, C and V flags according to the result.
Section
another 64-bit integer contained in R0 and R1, and place the result in R4 and R5.
Multiword values do not have to use consecutive registers.
that subtract a 96-bit integer contained in R9, R1, and R11 from another contained in R6,
R2, and R8. The example stores the result in R6, R9, and R2.
64-bit addition:
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– Rn must also be SP
– any shift in Operand2 must be limited to a maximum of 3 bits using LSL
Rn can be SP only in ADD and SUB
Rd can be PC only in the cond instruction where:
– you must not specify the S suffix
– Rm must not be PC and must not be SP
– if the instruction is conditional, it must be the last instruction in the IT block
with the exception of the cond instruction, Rn can be PC only in ADD and SUB, and only
with the additional restrictions:
– you must not specify the S suffix
– the second operand must be a constant in the range 0 to 4095.
When using the PC for an addition or a subtraction, bits[1:0] of the PC are rounded to
b00 before performing the calculation, making the base address for the calculation
word-aligned.
If you want to generate the address of an instruction, you have to adjust the constant
based on the value of the PC. ARM recommends that you use the ADR instruction
instead of ADD or SUB with Rn equal to the PC, because your assembler automatically
calculates the correct constant for the ADR instruction.
bit[0] of the value written to the PC is ignored
a branch occurs to the address created by forcing bit[0] of that value to 0.
shows two instructions that add a 64-bit integer contained in R2 and R3 to
ADD
SUBS
RSB
ADCHI
ADDS
ADC
All information provided in this document is subject to legal disclaimers.
R2, R1, R3
R8, R6, #240
R4, R4, #1280
R11, R0, R3
R4, R0, R2
R5, R1, R3
Rev. 2 — 19 August 2010
; add the least significant words
; add the most significant words with carry
; Sets the flags on the result
; Subtracts contents of R4 from 1280
; Only executed if C flag set and Z
; flag clear
Chapter 34: Appendix: Cortex-M3 user guide
Section
shows instructions
UM10360
© NXP B.V. 2010. All rights reserved.
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