LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 173

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
UM10360
User manual
received. The RxConsumeIndex is programmed by software and is the index of the next
descriptor that the software receive driver is going to process. When RxProduceIndex ==
RxConsumeIndex, the receive buffer is empty. When RxProduceIndex ==
RxConsumeIndex -1 (taking wraparound into account), the receive buffer is full and newly
received data would generate an overflow unless the software driver frees up one or more
descriptors.
Each receive descriptor takes two word locations (8 bytes) in memory. Likewise each
status field takes two words (8 bytes) in memory. Each receive descriptor consists of a
pointer to the data buffer for storing receive data (Packet) and a control word (Control).
The Packet field has a zero address offset, the control field has a 4 byte address offset
with respect to the descriptor address as defined in
Table 175. Receive Descriptor Fields
The data buffer pointer (Packet) is a 32-bit, byte aligned address value containing the
base address of the data buffer. The definition of the control word bits is listed in
Table
Table 176. Receive Descriptor Control Word
Table 177
Table 177. Receive Status Fields
Each receive status consists of two words. The StatusHashCRC word contains a
concatenation of the two 9-bit hash CRCs calculated from the destination and source
addresses contained in the received frame. After detecting the destination and source
addresses, StatusHashCRC is calculated once, then held for every fragment of the same
frame.
The concatenation of the two CRCs is shown in
Symbol
Packet
Control
Bit
10:0
30:11 -
31
Symbol
StatusInfo
StatusHashCRC 0x4
176.
Symbol
Size
Interrupt
lists the fields in the receive status elements from the status array.
All information provided in this document is subject to legal disclaimers.
Address
offset
0x0
0x4
Address
offset
0x0
Description
Size in bytes of the data buffer. This is the size of the buffer reserved by the
device driver for a frame or frame fragment i.e. the byte size of the buffer
pointed to by the Packet field. The size is -1 encoded e.g. if the buffer is 8
bytes the size field should be equal to 7.
Unused
If true generate an RxDone interrupt when the data in this frame or frame
fragment and the associated status information has been committed to
memory.
Rev. 2 — 19 August 2010
4
Bytes Description
4
Bytes Description
4
4
Base address of the data buffer for storing receive data.
Control information, see
Receive status return flags, see
The concatenation of the destination address hash CRC and
the source address hash CRC.
Table
Table
178:
Table
Chapter 10: LPC17xx Ethernet
175.
176.
Table
179.
UM10360
© NXP B.V. 2010. All rights reserved.
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