LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 807

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
Table 232. USB End of Transfer Interrupt Status register
Table 233. USB End of Transfer Interrupt Clear register
Table 234. USB End of Transfer Interrupt Set register
Table 235. USB New DD Request Interrupt Status register
Table 236. USB New DD Request Interrupt Clear register
Table 237. USB New DD Request Interrupt Set register
Table 238. USB System Error Interrupt Status register
Table 239. USB System Error Interrupt Clear register
Table 240. USB System Error Interrupt Set register
Table 241. SIE command code table. . . . . . . . . . . . . . . .245
Table 242. Set Address command bit description . . . . . .245
Table 243. Configure Device command bit description . .246
Table 244. Set Mode command bit description . . . . . . . .246
Table 245. Set Device Status command bit description. .247
Table 246. Get Error Code command bit description. . . .249
Table 247. Read Error Status command bit description .249
Table 248. Select Endpoint command bit description . . .250
Table 249. Set Endpoint Status command bit description251
Table 250. Clear Buffer command bit description . . . . . .252
Table 251. DMA descriptor . . . . . . . . . . . . . . . . . . . . . . .257
Table 252. USB (OHCI) related acronyms and abbreviations
Table 253. USB Host port pins . . . . . . . . . . . . . . . . . . . .271
Table 254. USB Host register address definitions . . . . .271
Table 255. USB OTG port pins . . . . . . . . . . . . . . . . . . . .275
Table 256. USB OTG and I2C register address definitions . .
Table 257. USB Interrupt Status register - (USBIntSt -
Table 258. OTG Interrupt Status register (OTGIntSt -
Table 259. OTG Status Control register (OTGStCtrl - address
Table 260. OTG Timer register (OTGTmr - address
Table 261. OTG clock control register (OTG_clock_control -
Table 262. OTG clock status register (OTGClkSt - address
UM10360
User manual
(USBDMAIntEn - address 0x5000 C294) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .239
(USBEoTIntSt - address 0x5000 C2A0s) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .239
(USBEoTIntClr - address 0x5000 C2A4) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .240
(USBEoTIntSet - address 0x5000 C2A8) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .240
(USBNDDRIntSt - address 0x5000 C2AC) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .240
(USBNDDRIntClr - address 0x5000 C2B0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .240
(USBNDDRIntSet - address 0x5000 C2B4) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .241
(USBSysErrIntSt - address 0x5000 C2B8) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .241
(USBSysErrIntClr - address 0x5000 C2BC) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .241
(USBSysErrIntSet - address 0x5000 C2C0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .241
used in this chapter . . . . . . . . . . . . . . . . . . . .269
277
address 0x5000 C1C0) bit description . . . . . .277
address 0x5000 C100) bit description . . . . . .278
0x5000 C110) bit description . . . . . . . . . . . . .279
0x5000 C114) bit description . . . . . . . . . . . . .280
address 0x5000 CFF4) bit description . . . . . .280
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Table 263. I2C Receive register (I2C_RX - address
Table 264. I2C Transmit register (I2C_TX - address
Table 265. I2C status register (I2C_STS - address
Table 266. I2C Control register (I2C_CTL - address
Table 267. I2C_CLKHI register (I2C_CLKHI - address
Table 268. I2C_CLKLO register (I2C_CLKLO - address
Table 269: UARTn Pin description . . . . . . . . . . . . . . . . . 299
Table 270. UART0/2/3 Register Map . . . . . . . . . . . . . . . 300
Table 271: UARTn Receiver Buffer Register (U0RBR -
Table 272: UARTn Transmit Holding Register (U0THR -
Table 273: UARTn Divisor Latch LSB register (U0DLL -
Table 274: UARTn Divisor Latch MSB register (U0DLM -
Table 275: UARTn Interrupt Enable Register (U0IER -
Table 276: UARTn Interrupt Identification Register (U0IIR -
Table 277: UARTn Interrupt Handling . . . . . . . . . . . . . . . 304
Table 278: UARTn FIFO Control Register (U0FCR - address
Table 279: UARTn Line Control Register (U0LCR - address
Table 280: UARTn Line Status Register (U0LSR - address
Table 281: UARTn Scratch Pad Register (U0SCR - address
Table 282: UARTn Auto-baud Control Register (U0ACR -
Table 283: UARTn IrDA Control Register (U0ICR - 0x4000
Table 284: IrDA Pulse Width . . . . . . . . . . . . . . . . . . . . . . 312
0x5000 CFF8) bit description. . . . . . . . . . . . . 281
0x5000 C300) bit description . . . . . . . . . . . . . 282
0x5000 C300) bit description . . . . . . . . . . . . . 282
0x5000 C304) bit description . . . . . . . . . . . . . 282
0x5000 C308) bit description . . . . . . . . . . . . . 284
0x5000 C30C) bit description. . . . . . . . . . . . . 285
0x5000 C310) bit description . . . . . . . . . . . . . 285
address 0x4000 C000, U2RBR - 0x4009 8000,
U3RBR - 04009 C000 when DLAB = 0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
address 0x4000 C000, U2THR - 0x4009 8000,
U3THR - 0x4009 C000 when DLAB = 0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
address 0x4000 C000, U2DLL - 0x4009 8000,
U3DLL - 0x4009 C000 when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
address 0x4000 C004, U2DLM - 0x4009 8004,
U3DLM - 0x4009 C004 when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
address 0x4000 C004, U2IER - 0x4009 8004,
U3IER - 0x4009 C004 when DLAB = 0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
address 0x4000 C008, U2IIR - 0x4009 8008,
U3IIR - 0x4009 C008) bit description. . . . . . . 303
0x4000 C008, U2FCR - 0x4009 8008, U3FCR -
0x4007 C008) bit description . . . . . . . . . . . . . 305
0x4000 C00C, U2LCR - 0x4009 800C, U3LCR -
0x4009 C00C) bit description. . . . . . . . . . . . . 306
0x4000 C014, U2LSR - 0x4009 8014, U3LSR -
0x4009 C014) bit description . . . . . . . . . . . . . 307
0x4000 C01C, U2SCR - 0x4009 801C, U3SCR -
0x4009 C01C) bit description. . . . . . . . . . . . . 308
address 0x4000 C020, U2ACR - 0x4009 8020,
U3ACR - 0x4009 C020) bit description . . . . . 308
C024, U2ICR - 0x4009 8024, U3ICR - 0x4009
C024) bit description . . . . . . . . . . . . . . . . . . . 311
Chapter 35: Supplementary information
UM10360
© NXP B.V. 2010. All rights reserved.
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