LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 466

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
19.10 Software example
UM10360
User manual
19.10.5.1 State: 0x00
19.10.1 Initialization routine
19.10.2 Start Master Transmit function
19.10.3 Start Master Receive function
19.10.4 I
19.10.5 Non mode specific states
Example to initialize I
Begin a Master Transmit operation by setting up the buffer, pointer, and data count, then
initiating a START.
Begin a Master Receive operation by setting up the buffer, pointer, and data count, then
initiating a START.
Determine the I
Bus Error. Enter not addressed Slave mode and release bus.
2
1. Load the I2ADR registers and I2MASK registers with values to configure the own
2. Enable I
3. Write 0x44 to I2CONSET to set the I2EN and AA bits, enabling Slave functions. For
1. Initialize Master data counter.
2. Set up the Slave Address to which data will be transmitted, and add the Write bit.
3. Write 0x20 to I2CONSET to set the STA bit.
4. Set up data to be transmitted in Master Transmit buffer.
5. Initialize the Master data counter to match the length of the message being sent.
6. Exit
1. Initialize Master data counter.
2. Set up the Slave Address to which data will be transmitted, and add the Read bit.
3. Write 0x20 to I2CONSET to set the STA bit.
4. Set up the Master Receive buffer.
5. Initialize the Master data counter to match the length of the message to be received.
6. Exit
1. Read the I
2. Use the status value to branch to one of 26 possible state routines.
C interrupt routine
Slave Address, enable General Call recognition if needed.
Master only functions, write 0x40 to I2CONSET.
2
C interrupt.
2
2
C status from I2STA.
All information provided in this document is subject to legal disclaimers.
C state and which state routine will be used to handle it.
2
C Interface as a Slave and/or Master.
Rev. 2 — 19 August 2010
Chapter 19: LPC17xx I2C0/1/2
UM10360
© NXP B.V. 2010. All rights reserved.
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