LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 581

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
29.6 Operation
UM10360
User manual
29.6.1 Hardware-triggered conversion
29.6.2 Interrupts
29.6.3 Accuracy vs. digital receiver
29.6.4 DMA control
Once an ADC conversion is started, it cannot be interrupted. A new software write to
launch a new conversion or a new edge-trigger event will be ignored while the previous
conversion is in progress.
If the BURST bit in the ADCR is 0 and the START field contains 010-111, the ADC will
start a conversion when a transition occurs on a selected pin or Timer Match signal. The
choices include conversion on a specified edge of any of 4 Match signals, or conversion
on a specified edge of either of 2 Capture/Match pins. The pin state from the selected pad
or the selected Match signal, XORed with ADCR bit 27, is used in the edge detection
logic.
An interrupt request is asserted to the NVIC when the DONE bit is 1. Software can use the
Interrupt Enable bit for the A/D Converter in the NVIC to control whether this assertion
results in an interrupt. DONE is negated when the ADDR is read.
The ADC function must be selected via the PINSEL registers in order to get accurate
voltage readings on the monitored pin. The PINMODE should also be set to the mode for
which neither pull-up nor pull-down resistor is enabled. For a pin hosting an ADC input, it
is not possible to have a have a digital function selected and yet get valid ADC readings.
An inside circuit disconnects ADC hardware from the associated pin whenever a digital
function is selected on that pin.
A DMA transfer request is generated from the ADC interrupt request line. To generate a
DMA transfer the same conditions must be met as the conditions for generating an
interrupt (see
Remark: If the DMA is used, the ADC interrupt must be disabled in the NVIC.
For DMA transfers, only burst requests are supported. The burst size can be set to one in
the DMA channel control register (see
not equal to one of the other DMA-supported burst sizes (applicable DMA burst sizes are
1, 4, 8 - see
The DMA transfer size determines when a DMA interrupt is generated. The transfer size
can be set to the number of ADC channels being converted (see
Non-contiguous channels can be transferred by the DMA using the scatter/gather linked
lists (see
Section
Section
Section 29.6.2
All information provided in this document is subject to legal disclaimers.
31.5.19).
31.5.20), set the burst size to one.
Rev. 2 — 19 August 2010
and
Chapter 29: LPC17xx Analog-to-Digital Converter (ADC)
Section
Section
29.5.3).
31.5.20). If the number of ADC channels is
Section
UM10360
© NXP B.V. 2010. All rights reserved.
31.5.20).
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