LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 243
LPC1759FBD80,551
Manufacturer Part Number
LPC1759FBD80,551
Description
IC ARM CORTEX MCU 512K 80-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1751FBD80551.pdf
(74 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
Specifications of LPC1759FBD80,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
80-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
52
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 6x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
52
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 6 Channel
On-chip Dac
10 bit
Package
80LQFP
Device Core
ARM Cortex M3
Family Name
LPC17xx
Maximum Speed
120 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4968
935290523551
935290523551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1759FBD80,551
Manufacturer:
LT
Quantity:
375
Company:
Part Number:
LPC1759FBD80,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
LPC1759FBD80,551
Manufacturer:
NXP/恩智浦
Quantity:
20 000
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NXP Semiconductors
UM10360
User manual
Fig 29. Interrupt event handling
USBEpIntEn[n]
interrupt
event on
EPn
For simplicity, USBDevIntEn and USBDMAIntEn are not shown.
USBEpIntSt
USBDMARSt
USBNDDRIntSt
USBSysErrIntSt
USBEoTIntST
n
USBEpIntPri[n]
n
31
31
31
0
0
0
from other
Endpoints
.
.
.
.
.
.
.
.
.
.
.
.
to DMA engine
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Slave mode
USBDMAIntSt
USBDevIntSt
DMA Mode
All information provided in this document is subject to legal disclaimers.
EP_SLOW
ERR_INT
EP_FAST
NDDR
FRAME
EOT
ERR
.
.
.
.
Rev. 2 — 19 August 2010
USBDevIntPri[0]
USBDevIntPri[1]
.
.
.
.
Chapter 11: LPC17xx USB device controller
USB_INT_REQ_DMA
USB_INT_REQ_HP
USB_INT_REQ_LP
EN_USB_INTS
USBIntSt
UM10360
© NXP B.V. 2010. All rights reserved.
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