LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 261

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
UM10360
User manual
11.15.5.5 Ending the packet transfer
11.15.5.6 No_Packet DD
11.15.6.1 Setting up DMA transfers
11.15.6 Isochronous endpoint operation
The DMA_PROCEED flag is cleared after the required number of bytes specified in the
DMA_buffer_length field is transferred. It is also cleared when the software writes into the
USBEpDMADis register. The ability to clear the DMA_PROCEED flag allows software to
to force the DD to be re-fetched for the next packet transfer. Writing all zeros into the
USBEpDMADis register clears the DMA_PROCEED flag without disabling DMA operation
for any endpoint.
On completing a packet transfer, the DMA engine writes back the DD with updated status
information to the same memory location from where it was read. The
DMA_buffer_start_addr, Present_DMA_count, and the DD_status fields in the DD are
updated.
A DD can have the following types of completion:
For an IN transfer, if the system does not have any data to send for a while, it can respond
to an NDDR interrupt by programming a No_Packet DD. This is done by setting both the
Max_packet_size and DMA_buffer_length fields in the DD to 0. On processing a
No_Packet DD, the DMA engine clears the DMA request bit in USBDMARSt
corresponding to the endpoint without transferring a packet. The DD is retired with a
status code of NormalCompletion. This can be repeated as often as necessary. The
device will respond to IN token packets on the USB bus with a NAK until a DD with a data
packet is programmed and the DMA transfers the packet into the endpoint buffer.
For isochronous endpoints, the packet size can vary for each packet. There is one packet
per isochronous endpoint for each frame.
Software sets the isochronous endpoint bit to 1 in the DD, and programs the initial value of
the Isochronous_packetsize_memory_address field. All other fields are initialized the
same as for non-isochronous endpoints.
Normal completion - If the current packet is fully transferred and the
Present_DMA_count field equals the DMA_buffer_length, the DD has completed
normally. The DD will be written back to memory with DD_retired set and DD_status set
to NormalCompletion. The EOT interrupt is raised for this endpoint.
USB transfer end completion - If the current packet is fully transferred and its size is
less than the Max_packet_size field, and the end of the DMA buffer is still not reached,
the USB transfer end completion occurs. The DD will be written back to the memory
with DD_retired set and DD_Status set to the DataUnderrun completion code. The EOT
interrupt is raised for this endpoint.
Error completion - If the current packet is partially transferred i.e. the end of the DMA
buffer is reached in the middle of the packet transfer, an error situation occurs. The DD
is written back with DD_retired set and DD_status set to the DataOverrun status code.
The EOT interrupt is raised for this endpoint and the corresponding bit in USBEpDMASt
register is cleared. The packet will be re-sent from the endpoint buffer to memory when
the corresponding EPxx_DMA_ENABLE bit is set again using the USBEpDMAEn
register.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 11: LPC17xx USB device controller
UM10360
© NXP B.V. 2010. All rights reserved.
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