LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 512

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
24.4 Sample waveform with rules for single and double edge control
UM10360
User manual
A sample of how PWM values relate to waveform outputs is shown in
output logic is shown in
controlled PWM outputs via the muxes controlled by the PWMSELn bits. The match
register selections for various PWM outputs is shown in
supports up to N-1 single edge PWM outputs or (N-1)/2 double edge PWM outputs, where
N is the number of match registers that are implemented. PWM types can be mixed if
desired.
Table 443. Set and reset inputs for PWM Flip-Flops
[1]
[2]
PWM Channel
1
2
3
4
5
6
Fig 120. Sample PWM waveforms
Identical to single edge mode in this case since Match 0 is the neighboring match register. Essentially,
PWM1 cannot be a double edged output.
It is generally not advantageous to use PWM channels 3 and 5 for double edge PWM outputs because it
would reduce the number of double edge PWM outputs that are possible. Using PWM 2, PWM4, and
PWM6 for double edge PWM outputs provides the most pairings.
The waveforms below show a single PWM cycle and demonstrate PWM outputs under the
following conditions:
The timer is configured for PWM mode (counter resets to 1).
Match 0 is configured to reset the timer/counter when a match event occurs.
All PWM related Match registers are configured for toggle on match.
Control bits PWMSEL2 and PWMSEL4 are set.
The Match register values are as follows:
MR0 = 100 (PWM rate)
MR1 = 41, MR2 = 78 (PWM2 output)
MR3 = 53, MR4 = 27 (PWM4 output)
MR5 = 65 (PWM5 output)
All information provided in this document is subject to legal disclaimers.
PWM2
PWM4
PWM5
Single Edge PWM (PWMSELn = 0)
Set by
Match 0
Match 0
Match 0
Match 0
Match 0
Match 0
Rev. 2 — 19 August 2010
Figure 119
1
Chapter 24: LPC17xx Pulse Width Modulator (PWM)
27
that allows selection of either single or double edge
Reset by
Match 1
Match 2
Match 3
Match 4
Match 5
Match 6
41
53
65
Double Edge PWM (PWMSELn = 1)
Set by
Match 0
Match 1
Match 2
Match 3
Match 4
Match 5
78
Table
(counter is reset)
[1]
[2]
[2]
443. This implementation
100
UM10360
Figure
© NXP B.V. 2010. All rights reserved.
Match 2
Match 4
Match 6
Reset by
Match 1
Match 3
Match 5
120. PWM
[1]
[2]
[2]
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