LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 370

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
Table 335. CAN Sleep Clear register (CANSLEEPCLR - address 0x400F C110) bit description
Table 336. CAN Wake-up Flags register (CANWAKEFLAGS - address 0x400F C114) bit description
16.8 CAN controller operation
UM10360
User manual
Bit
0
1
2
31:3
Bit
0
1
2
31:3
Symbol
-
CAN1SLEEP
CAN2SLEEP
-
Symbol
-
CAN1WAKE
CAN2WAKE
-
16.7.18 CAN Wake-up Flags register (CANWAKEFLAGS - 0x400F C114)
16.8.1 Error handling
Function
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Sleep status and control for CAN channel 1.
Read: when 1, indicates that CAN channel 1 is in the sleep mode.
Write: writing a 1 causes clocks to be restored to CAN channel 1.
Sleep status and control for CAN channel 2.
Read: when 1, indicates that CAN channel 2 is in the sleep mode.
Write: writing a 1 causes clocks to be restored to CAN channel 2.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Function
Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
Wake-up status for CAN channel 1
Read: when 1, indicates that a falling edge has occurred on the receive data line of
CAN channel 1.
Write: writing a 1 clears this bit.
Wake-up status for CAN channel 2
Read: when 1, indicates that a falling edge has occurred on the receive data line of
CAN channel 2.
Write: writing a 1 clears this bit.
Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
This register provides the wake-up status for the two CAN channels and allows clearing
wake-up events. Refer to
sleep feature.
The CAN Controllers count and handle transmit and receive errors as specified in CAN
Spec 2.0B. The Transmit and Receive Error Counters are incriminated for each detected
error and are decremented when operation is error-free. If the Transmit Error counter
contains 255 and another error occurs, the CAN Controller is forced into a state called
Bus-Off. In this state, the following register bits are set: BS in CANxSR, BEI and EI in
CANxIR if these are enabled, and RM in CANxMOD. RM resets and disables much of the
CAN Controller. Also at this time the Transmit Error Counter is set to 127 and the Receive
Error Counter is cleared. Software must next clear the RM bit. Thereafter the Transmit
Error Counter will count down 128 occurrences of the Bus Free condition (11 consecutive
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Section 16.8.2 “Sleep mode”
.
.
for more information on the CAN
Chapter 16: LPC17xx CAN1/2
UM10360
© NXP B.V. 2010. All rights reserved.
Reset Value
NA
0
0
NA
Reset Value
NA
0
0
NA
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