LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 673
LPC1759FBD80,551
Manufacturer Part Number
LPC1759FBD80,551
Description
IC ARM CORTEX MCU 512K 80-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1751FBD80551.pdf
(74 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
Specifications of LPC1759FBD80,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
80-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
52
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 6x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
52
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 6 Channel
On-chip Dac
10 bit
Package
80LQFP
Device Core
ARM Cortex M3
Family Name
LPC17xx
Maximum Speed
120 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4968
935290523551
935290523551
Available stocks
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Quantity
Price
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NXP Semiconductors
UM10360
User manual
34.2.4.7.1 Syntax
34.2.4.7.2 Operation
34.2.4.7.3 Restrictions
34.2.4.7.4 Condition flags
34.2.4.7.5 Examples
34.2.4.7 PUSH and POP
Push registers onto, and pop registers off a full-descending stack.
PUSH{cond} reglist
POP{cond} reglist
where:
cond is an optional condition code, see
reglist is a non-empty list of registers, enclosed in braces. It can contain register ranges. It
must be comma separated if it contains more than one register or register range.
PUSH and POP are synonyms for STMDB and LDM (or LDMIA) with the memory addresses for the
access based on SP, and with the final address for the access written back to the SP. PUSH
and POP are the preferred mnemonics in these cases.
PUSH stores registers on the stack in order of decreasing the register numbers, with the
highest numbered register using the highest memory address and the lowest numbered
register using the lowest memory address.
POP loads registers from the stack in order of increasing register numbers, with the lowest
numbered register using the lowest memory address and the highest numbered register
using the highest memory address.
See
In these instructions:
When PC is in reglist in a POP instruction:
These instructions do not change the flags.
•
•
•
•
•
reglist must not contain SP
for the PUSH instruction, reglist must not contain PC
for the POP instruction, reglist must not contain PC if it contains LR.
bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch
occurs to this halfword-aligned address
if the instruction is conditional, it must be the last instruction in the IT block.
Section 34.2.4.6
PUSH
PUSH
POP
All information provided in this document is subject to legal disclaimers.
{R0,R4-R7}
{R2,LR}
{R0,R10,PC}
for more information.
Rev. 2 — 19 August 2010
Section 34.2.3.7 “Conditional
Chapter 34: Appendix: Cortex-M3 user guide
execution”.
UM10360
© NXP B.V. 2010. All rights reserved.
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