LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 809

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
Table 336. CAN Wake-up Flags register (CANWAKEFLAGS
Table 337. Central Transit Status Register (CANTxSR -
Table 338. Central Receive Status Register (CANRxSR -
Table 339. Central Miscellaneous Status Register (CANMSR
Table 340. Acceptance filter modes and access control .373
Table 341. Section configuration register settings . . . . . .374
Table 342. Acceptance Filter Mode Register (AFMR -
Table 343. Standard Frame Individual Start Address register
Table 344. Standard Frame Group Start Address register
Table 345. Extended Frame Start Address register (EFF_sa
Table 346. Extended Frame Group Start Address register
Table 347. End of AF Tables register (ENDofTable - address
Table 348. LUT Error Address register (LUTerrAd - address
Table 349. LUT Error register (LUTerr - address
Table 350. Global FullCAN Enable register (FCANIE -
Table 351. FullCAN Interrupt and Capture register 0
Table 352. FullCAN Interrupt and Capture register 1
Table 353. Format of automatically stored Rx messages 384
Table 354. FullCAN semaphore operation. . . . . . . . . . . .384
Table 355. Example of Acceptance Filter Tables and ID index
Table 356. Used ID-Look-up Table sections . . . . . . . . . .396
Table 357. Used ID-Look-up Table sections . . . . . . . . . .397
Table 358. SPI pin description . . . . . . . . . . . . . . . . . . . . .402
Table 359. SPI Data To Clock Phase Relationship . . . . .403
Table 360. SPI register map . . . . . . . . . . . . . . . . . . . . . .406
Table 361: SPI Control Register (S0SPCR - address
Table 362: SPI Status Register (S0SPSR - address
Table 363: SPI Data Register (S0SPDR - address
Table 364: SPI Clock Counter Register (S0SPCCR - address
Table 365: SPI Test Control Register (SPTCR - address
Table 366: SPI Test Status Register (SPTSR - address
UM10360
User manual
- address 0x400F C114) bit description . . . . .370
address 0x4004 0000) bit description. . . . . . .372
address 0x4004 0004) bit description. . . . . . .372
- address 0x4004 0008) bit description . . . . .373
address 0x4003 C000) bit description . . . . . .377
(SFF_sa - address 0x4003 C004) bit description .
378
(SFF_GRP_sa - address 0x4003 C008) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .378
- address 0x4003 C00C) bit description . . . . .378
(EFF_GRP_sa - address 0x4003 C010) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .379
0x4003 C014) bit description . . . . . . . . . . . . .379
0x4003 C018) bit description . . . . . . . . . . . . .380
0x4003 C01C) bit description . . . . . . . . . . . . .380
address 0x4003 C020) bit description . . . . . .380
(FCANIC0 - address 0x4003 C024) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .380
(FCANIC1 - address 0x4003 C028) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .381
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .394
0x4002 0000) bit description . . . . . . . . . . . . .407
0x4002 0004) bit description . . . . . . . . . . . . .408
0x4002 0008) bit description . . . . . . . . . . . . .408
0x4002 000C) bit description . . . . . . . . . . . . .409
0x4002 0010) bit description . . . . . . . . . . . . .409
0x4002 0014) bit description . . . . . . . . . . . . .409
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Table 367: SPI Interrupt Register (S0SPINT - address
Table 368. SSP pin descriptions . . . . . . . . . . . . . . . . . . . 413
Table 369. SSP Register Map. . . . . . . . . . . . . . . . . . . . . 421
Table 370: SSPn Control Register 0 (SSP0CR0 - address
Table 371: SSPn Control Register 1 (SSP0CR1 - address
Table 372: SSPn Data Register (SSP0DR - address
Table 373: SSPn Status Register (SSP0SR - address
Table 374: SSPn Clock Prescale Register (SSP0CPSR -
Table 375: SSPn Interrupt Mask Set/Clear register
Table 376: SSPn Raw Interrupt Status register (SSP0RIS -
Table 377: SSPn Masked Interrupt Status register (SSPnMIS
Table 378: SSPn interrupt Clear Register (SSP0ICR -
Table 379: SSPn DMA Control Register (SSP0DMACR -
Table 380. I
Table 381. I2C0CONSET and I2C1CONSET used to
Table 382. I2C0CONSET and I2C1CONSET used to
Table 383. I
Table 384. I
Table 385. I
Table 386. I
Table 387. I
Table 388. I
0x4002 001C) bit description . . . . . . . . . . . . . 410
0x4008 8000, SSP1CR0 - 0x4003 0000) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
0x4008 8004, SSP1CR1 - 0x4003 0004) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
0x4008 8008, SSP1DR - 0x4003 0008) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
0x4008 800C, SSP1SR - 0x4003 000C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
address 0x4008 8010, SSP1CPSR -
0x4003 0010) bit description . . . . . . . . . . . . . 424
(SSP0IMSC - address 0x4008 8014, SSP1IMSC -
0x4003 0014) bit description . . . . . . . . . . . . . 425
address 0x4008 8018, SSP1RIS - 0x4003 0018)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 425
-address 0x4008 801C, SSP1MIS -
0x4003 001C) bit description . . . . . . . . . . . . . 426
address 0x4008 8020, SSP1ICR - 0x4003 0020)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 426
address 0x4008 8024, SSP1DMACR -
0x4003 0024) bit description . . . . . . . . . . . . . 427
configure Master mode . . . . . . . . . . . . . . . . . 431
configure Slave mode . . . . . . . . . . . . . . . . . . 433
I2C0CONSET - address 0x4001 C000, I
I2C1CONSET - address 0x4005 C000, I
I2C2CONSET - address 0x400A 0000) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
I2C0CONCLR - 0x4001 C018; I
I2C1CONCLR - 0x4005 C018; I
I2C2CONCLR - 0x400A 0018) bit description 442
0x4001 C004; I
I
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
0x4001 C008; I
I
I
2
2
2
2
2
2
2
2
2
2
C2, I2C2STAT - 0x400A 0004) bit
C2, I2C2DAT - 0x400A 0008) bit description444
C0, I2C0MMCTRL - 0x4001 C01C; I
C Pin Description . . . . . . . . . . . . . . . . . . . . 430
C register map . . . . . . . . . . . . . . . . . . . . . . 439
C Control Set register (I2CONSET: I
C Control Clear register (I2CONCLR: I
C Status register (I2STAT: I
C Data register (I2DAT: I
C Monitor mode control register (I2MMCTRL:
Chapter 35: Supplementary information
2
2
C1, I2C1STAT - 0x4005 C004;
C1, I2C1DAT - 0x4005 C008;
2
C0, I2C0DAT -
UM10360
© NXP B.V. 2010. All rights reserved.
2
C0, I2C0STAT -
2
2
C1,
C2,
2
2
C1,
C0,
809 of 840
2
2
2
C1,
C2,
C0,