LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 168

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
10.14 Module control register definitions
UM10360
User manual
10.13.5 Hash Filter Table MSBs Register (HashFilterH - 0x5000 0214)
10.14.1 Interrupt Status Register (IntStatus - 0x5000 0FE0)
The Hash Filter table MSBs register (HashFilterH) has an address of 0x5000 0214.
Table 169
found in
Table 169. Hash Filter MSBs register (HashFilterH - address 0x5000 0214) bit description
The Interrupt Status register (IntStatus) is a read-only register with an address of
0x5000 0FE0. The interrupt status register bit definition is shown in
all bits are flip-flops with an asynchronous set in order to be able to generate interrupts if
there are wake-up events while clocks are disabled.
Table 170. Interrupt Status register (IntStatus - address 0x5000 0FE0) bit description
Bit
31:0
Bit
0
1
2
3
4
5
6
7
11:8
12
13
31:14 -
Symbol
HashFilterH
Symbol
RxOverrunInt
RxErrorInt
RxFinishedInt
RxDoneInt
TxUnderrunInt Interrupt set on a fatal underrun error in the transmit queue. The
TxErrorInt
TxFinishedInt
TxDoneInt
-
SoftInt
WakeupInt
Section 10.17.10 “Receive filtering” on page
lists the bit definitions of the register. Details of Hash filter table use can be
All information provided in this document is subject to legal disclaimers.
Function
Interrupt set on a fatal overrun error in the receive queue. The
fatal interrupt should be resolved by a Rx soft-reset. The bit is not
set when there is a nonfatal overrun error.
Interrupt trigger on receive errors: AlignmentError, RangeError,
LengthError, SymbolError, CRCError or NoDescriptor or Overrun.
Interrupt triggered when all receive descriptors have been
processed i.e. on the transition to the situation where
ProduceIndex == ConsumeIndex.
Interrupt triggered when a receive descriptor has been processed
while the Interrupt bit in the Control field of the descriptor was set.
fatal interrupt should be resolved by a Tx soft-reset. The bit is not
set when there is a nonfatal underrun error.
Interrupt trigger on transmit errors: LateCollision,
ExcessiveCollision and ExcessiveDefer, NoDescriptor or
Underrun.
Interrupt triggered when all transmit descriptors have been
processed i.e. on the transition to the situation where
ProduceIndex == ConsumeIndex.
Interrupt triggered when a descriptor has been transmitted while
the Interrupt bit in the Control field of the descriptor was set.
Unused
Interrupt triggered by software writing a 1 to the SoftintSet bit in
the IntSet register.
Interrupt triggered by a Wake-up event detected by the receive
filter.
Unused
Rev. 2 — 19 August 2010
Function
Bits 63:32 of the imperfect filter hash table for receive
filtering.
198.
Chapter 10: LPC17xx Ethernet
Table
UM10360
© NXP B.V. 2010. All rights reserved.
170. Note that
168 of 840
Reset
value
0x0
Reset
value
0
0
0
0
0
0
0
0
0x0
0
0
0x0