LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 182
LPC1759FBD80,551
Manufacturer Part Number
LPC1759FBD80,551
Description
IC ARM CORTEX MCU 512K 80-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1751FBD80551.pdf
(74 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
Specifications of LPC1759FBD80,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
80-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
52
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 6x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
52
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 6 Channel
On-chip Dac
10 bit
Package
80LQFP
Device Core
ARM Cortex M3
Family Name
LPC17xx
Maximum Speed
120 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4968
935290523551
935290523551
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UM10360
User manual
10.17.3 Transmit process
Please note that the transmit descriptors, receive descriptors and receive statuses are 8
bytes each while the transmit statuses are 4 bytes each. All descriptor arrays and transmit
statuses need to be aligned on 4 byte boundaries; receive status arrays need to be
aligned on 8 byte boundaries. The number of descriptors in the descriptor arrays needs to
be written to the TxDescriptorNumber/RxDescriptorNumber registers using a -1 encoding
i.e. the value in the registers is the number of descriptors minus one e.g. if the descriptor
array has 4 descriptors the value of the number of descriptors register should be 3.
After setting up the descriptor arrays, frame buffers need to be allocated for the receive
descriptors before enabling the receive data path. The Packet field of the receive
descriptors needs to be filled with the base address of the frame buffer of that descriptor.
Amongst others the Control field in the receive descriptor needs to contain the size of the
data buffer using -1 encoding.
The receive data path has a configurable filtering function for discarding/ignoring specific
Ethernet frames. The filtering function should also be configured during initialization.
After an assertion of the hardware reset, the soft reset bit in the MAC will be asserted. The
soft reset condition must be removed before the Ethernet block can be enabled.
Enabling of the receive function is located in two places. The receive DMA manager
needs to be enabled and the receive data path of the MAC needs to be enabled. To
prevent overflow in the receive DMA engine the receive DMA engine should be enabled
by setting the RxEnable bit in the Command register before enabling the receive data path
in the MAC by setting the RECEIVE ENABLE bit in the MAC1 register.
The transmit DMA engine can be enabled at any time by setting the TxEnable bit in the
Command register.
Before enabling the data paths, several options can be programmed in the MAC, such as
automatic flow control, transmit to receive loop-back for verification, full/half duplex
modes, etc.
Base addresses of descriptor arrays and descriptor array sizes cannot be modified
without a (soft) reset of the receive and transmit data paths.
Overview
This section outlines the transmission process.
Device driver sets up descriptors and data
If the descriptor array is full the device driver should wait for the descriptor arrays to
become not full before writing to a descriptor in the descriptor array. If the descriptor array
is not full, the device driver should use the descriptor numbered TxProduceIndex of the
array pointed to by TxDescriptor.
The Packet pointer in the descriptor is set to point to a data frame or frame fragment to be
transmitted. The Size field in the Command field of the descriptor should be set to the
number of bytes in the fragment buffer, -1 encoded. Additional control information can be
indicated in the Control field in the descriptor (bits Interrupt, Last, CRC, Pad).
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 10: LPC17xx Ethernet
UM10360
© NXP B.V. 2010. All rights reserved.
182 of 840
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