LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 219
LPC1759FBD80,551
Manufacturer Part Number
LPC1759FBD80,551
Description
IC ARM CORTEX MCU 512K 80-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1751FBD80551.pdf
(74 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
Specifications of LPC1759FBD80,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
80-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
52
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 6x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
52
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 6 Channel
On-chip Dac
10 bit
Package
80LQFP
Device Core
ARM Cortex M3
Family Name
LPC17xx
Maximum Speed
120 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4968
935290523551
935290523551
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UM10360
User manual
11.9.3 Power management support
Table 187. USB device controller clock sources
To help conserve power, the USB device controller automatically disables the AHB master
clock and usbclk when not in use.
When the USB Device Controller goes into the suspend state (bus is idle for 3 ms), the
usbclk input to the device controller is automatically disabled, helping to conserve power.
However, if software wishes to access the device controller registers, usbclk must be
active. To allow access to the device controller registers while in the suspend state, the
USBClkCtrl and USBClkSt registers are provided.
When software wishes to access the device controller registers, it should first ensure
usbclk is enabled by setting DEV_CLK_EN in the USBClkCtrl register, and then poll the
corresponding DEV_CLK_ON bit in USBClkSt until set. Once set, usbclk will remain
enabled until DEV_CLK_EN is cleared by software.
When a DMA transfer occurs, the device controller automatically turns on the AHB master
clock. Once asserted, it remains active for a minimum of 2 ms (2 frames), to help ensure
that DMA throughput is not affected by turning off the AHB master clock. 2 ms after the
last DMA access, the AHB master clock is automatically disabled to help conserve power.
If desired, software also has the capability of forcing this clock to remain enabled using the
USBClkCtrl register.
Note that the AHB slave clock is always enabled as long as the PCUSB bit of PCONP is
set. When the device controller is not in use, all of the device controller clocks may be
disabled by clearing PCUSB.
The USB_NEED_CLK signal is used to facilitate going into and waking up from chip
Power-down mode. USB_NEED_CLK is asserted if any of the bits of the USBClkSt
register are asserted.
After entering the suspend state with DEV_CLK_EN and AHB_CLK_EN cleared, the
DEV_CLK_ON and AHB_CLK_ON will be cleared when the corresponding clock turns off.
When both bits are zero, USB_NEED_CLK will be low, indicating that the chip can be put
into Power-down mode by writing to the PCON register. The status of USB_NEED_CLK
can be read from the USBIntSt register.
Any bus activity in the suspend state will cause the USB_NEED_CLK signal to be
asserted. When the chip is in Power-down mode and the USB interrupt is enabled, the
assertion of USB_NEED_CLK causes the chip to wake up from Power-down mode.
Clock source
AHB master clock
AHB slave clock
usbclk
All information provided in this document is subject to legal disclaimers.
Description
Clock for the AHB master bus interface and DMA
Clock for the AHB slave interface
48 MHz clock from the dedicated USB PLL (PLL1) or the Main PLL (PLL0),
used to recover the 12 MHz clock from the USB bus
Rev. 2 — 19 August 2010
Chapter 11: LPC17xx USB device controller
UM10360
© NXP B.V. 2010. All rights reserved.
219 of 840
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