LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 456

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
UM10360
User manual
Fig 96. Format and states in the Slave Transmitter mode
reception of the own
Slave address and
one or more Data
bytes all are
acknowledged
last data byte
transmitted. Switched
to Not Addressed
Slave (AA bit in
I2CON = “0”)
arbitration lost as
Master and
addressed as Slave
19.9.4 Slave Transmitter mode
DATA
n
In the slave transmitter mode, a number of data bytes are transmitted to a master receiver
(see
and I2CON have been initialized, the I
address followed by the data direction bit which must be “1” (R) for the I
operate in the slave transmitter mode. After its own slave address and the R bit have been
received, the serial interrupt flag (SI) is set and a valid status code can be read from
I2STAT. This status code is used to vector to a state service routine, and the appropriate
action to be taken for each of these status codes is detailed in
transmitter mode may also be entered if arbitration is lost while the I
master mode (see state 0xB0).
If the AA bit is reset during a transfer, the I
and enter state 0xC0 or 0xC8. The I
and will ignore the master receiver if it continues the transfer. Thus the master receiver
receives all 1s as serial data. While AA is reset, the I
slave address or a General Call address. However, the I
address recognition may be resumed at any time by setting AA. This means that the AA
bit may be used to temporarily isolate the I
A
Figure
S
from Master to Slave
from Slave to Master
any number of data bytes and their associated
Acknowledge bits
this number (contained in I2STA) corresponds to a defined state of
the I
96). Data transfer is initialized as in the slave receiver mode. When I2ADR
2
C bus
SLA
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
R
A8H
B0H
A
A
DATA
2
C block is switched to the not addressed slave mode
2
C block waits until it is addressed by its own slave
B8H
2
C block will transmit the last byte of the transfer
A
2
C block from the I
DATA
2
C block does not respond to its own
C8H
C0H
2
A
A
C-bus is still monitored, and
Chapter 19: LPC17xx I2C0/1/2
P OR S
ALL ONES
2
C-bus.
Table
2
401. The slave
C block is in the
UM10360
P OR S
© NXP B.V. 2010. All rights reserved.
2
C block to
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