LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 68

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

5.1 Introduction
5.2 Flash accelerator blocks
UM10360
User manual
Fig 13. Simplified block diagram of the flash accelerator showing potential bus connections
Cortex-M3
Controller
Purpose
General
5.2.1 Flash memory bank
DMA
CPU
Master Port
The flash accelerator block in the LPC17xx allows maximization of the performance of the
Cortex-M3 processor when it is running code from flash memory, while also saving power.
The flash accelerator also provides speed and power improvements for data accesses to
the flash memory.
The flash accelerator is divided into several functional blocks:
Figure 13
In the following descriptions, the term “fetch” applies to an explicit flash read request from
the CPU. “Prefetch” is used to denote a flash read of instructions beyond the current
processor fetch address.
There is one bank of flash memory controlled by the LPC17xx flash accelerator.
Flash programming operations are not controlled by the flash accelerator, but are handled
as a separate function. A Boot ROM contains flash programming algorithms that may be
called as part of the application program, and a loader that may be run to allow
programming of the flash memory.
DCode
•
•
•
•
ICode
DMA
bus
bus
UM10360
Chapter 5: LPC17xx Flash accelerator
Rev. 2 — 19 August 2010
AHB-Lite bus interface, accessible by the Cortex-M3 I-code and D-code buses, as
well as by the General Purpose DMA Controller
An array of eight 128-bit buffers
Flash accelerator control logic, including address compare and flash control
A flash memory interface
Matrix
shows a simplified diagram of the flash accelerator blocks and data paths.
Bus
Combined
All information provided in this document is subject to legal disclaimers.
AHB
Rev. 2 — 19 August 2010
Flash Accelerator
bus interface
AHB-Lite
Accelerator
Control
Buffer
Array
Flash
Interface
Flash
Memory
Flash
© NXP B.V. 2010. All rights reserved.
User manual
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