MCHC908JW32FAE Freescale Semiconductor, MCHC908JW32FAE Datasheet - Page 120

• Manufacturer Part Number: MCHC908JW32FAE
• Description: IC MCU 32K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908JW32FAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, USB
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 48
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: HC08JW
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, USB
• Number Of Programmable I/os: 29
• Number Of Timers: 2
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Timer Interface Module (TIM)
CHxMAX — Channel x Maximum Duty Cycle Bit
8.9.5 TIM Channel Registers
These read/write registers contain the captured TIM counter value of the input capture function or the
output compare value of the output compare function. The state of the TIM channel registers after reset
is unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH)
inhibits input captures until the low byte (TCHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIM channel x registers
(TCHxH) inhibits output compares until the low byte (TCHxL) is written.
120
When the TOVx bit is at logic 1, setting the CHxMAX bit forces the duty cycle of buffered and
unbuffered PWM signals to 100%. As
after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is
cleared.
Address: $0011
Address: $0012
When TOVx is set, a TIM counter overflow takes precedence over a
channel x output compare if both occur at the same time.
CHxMAX
Reset:
Reset:
Read:
Read:
Write:
Write:
TCHx
OVERFLOW
Bit 15
Bit 7
Bit 7
Bit 7
Figure 8-12. TIM Channel 0 Register High (TCH0H)
Figure 8-13. TIM Channel 0 Register Low (TCH0L)
COMPARE
PERIOD
OUTPUT
14
6
6
6
OVERFLOW
Figure 8-11. CHxMAX Latency
MC68HC908JW32 Data Sheet, Rev. 6
Figure 8-11
13
5
5
5
COMPARE
OUTPUT
Indeterminate after reset
Indeterminate after reset
NOTE
OVERFLOW
12
4
4
4
shows, the CHxMAX bit takes effect in the cycle
COMPARE
OUTPUT
11
3
3
3
OVERFLOW
10
2
2
2
COMPARE
OUTPUT
OVERFLOW
1
9
1
1
Freescale Semiconductor
Bit 0
Bit 8
Bit 0
Bit 0