MCHC908JW32FAE Freescale Semiconductor, MCHC908JW32FAE Datasheet - Page 76

• Manufacturer Part Number: MCHC908JW32FAE
• Description: IC MCU 32K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908JW32FAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, USB
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 48
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: HC08JW
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, USB
• Number Of Programmable I/os: 29
• Number Of Timers: 2
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

System Integration Module (SIM)
76
$FE00
$FE01
$FE03
Addr.
PIN LOGIC
RESET
Note: Writing a logic 0 clears SBSW.
SIM Reset Status Register
SIM Break Status Register
Register Name
SIM Break Flag Control
Register (SBFCR)
V
DD
INTERNAL
PULLUP
DEVICE
(SRSR)
(SBSR)
SIM RESET STATUS REGISTER
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
POR:
RESET PIN CONTROL
Figure 6-2. SIM I/O Register Summary
POR CONTROL
AND PRIORITY DECODE
STOP/WAIT
INTERRUPT CONTROL
CONTROL
CONTROL
CLOCK
BCFE
Bit 7
POR
Figure 6-1. SIM Block Diagram
MC68HC908JW32 Data Sheet, Rev. 6
R
1
0
0
= Unimplemented
PIN
6
R
R
CLOCK GENERATORS
0
0
RESET
COUNTER
SIM
COP
÷ 2
5
R
R
0
0
CONTROL
MASTER
RESET
ILOP
R
4
R
R
0
0
= Reserved
ILAD
R
R
3
0
0
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO CGM, OSC)
COP CLOCK
CGMXCLK (FROM CGM)
CGMOUT (FROM CGM)
INTERNAL CLOCKS
LVI (FROM LVI MODULE)
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP (FROM COP MODULE)
INTERRUPT SOURCES
CPU INTERFACE
USB
R
R
2
0
0
Freescale Semiconductor
SBSW
NOTE
LVI
R
1
0
0
Bit 0
R
R
0
0
0