MCHC908JW32FAE Freescale Semiconductor, MCHC908JW32FAE Datasheet - Page 165

• Manufacturer Part Number: MCHC908JW32FAE
• Description: IC MCU 32K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908JW32FAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, USB
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 48
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: HC08JW
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, USB
• Number Of Programmable I/os: 29
• Number Of Timers: 2
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

PRE — Prescaler Selection
CSEL[1:0] — Clock Frequency Selection bits.
PS2IEN — PS2 Interrupt Mask
CLKEN — Clock Output Enable bit
PS2EN — PS2 Clock Generator Module Enable
Freescale Semiconductor
These bits select prescaler divider ratio. Reset clears this bit.
These bits selects the clock divider ratio to cater for different clock source frequency. Reset clears
these bits.
This read/write bit enables the periodic PS2 interrupt. Reset clears this bit.
This read/write bit enables the open drain clock output. Reset clears this bit.
This read/write bit enables the module clock source. Reset clears this bit.
1 = Divide by 480 is selected
0 = Divide by 160 is selected
1 = PS2 interrupt is enabled
0 = PS2 interrupt is disabled
1 = Open drain clock output is enabled
0 = Open drain clock output is disabled
1 = Module enabled
0 = Module disabled
Glitches may occur when CSEL[1:0] and PRE value can be altered while
PS2EN is set.
Frequency
8-MHz
6-MHz
4-MHz
BUS
Table 12-2. Clock Selection Summary
Table 12-1. CSEL[1:0] Divider Ratio
(Divider Raito)
MC68HC908JW32 Data Sheet, Rev. 6
CSEL[1:0]
PRE
160
480
160
00
01
10
11
NOTE
(Divider Ratio)
CSEL[1:0]
Divider Ratio
Not used
4
1
2
PS2 Clock Generator Control and Status Registers
1
2
4
Port Output
Frequency
12.5 kHz
12.5 kHz
12.5 kHz
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