MCHC908JW32FAE Freescale Semiconductor, MCHC908JW32FAE Datasheet - Page 185

• Manufacturer Part Number: MCHC908JW32FAE
• Description: IC MCU 32K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908JW32FAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, USB
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 48
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: HC08JW
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, USB
• Number Of Programmable I/os: 29
• Number Of Timers: 2
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Chapter 14
External Interrupt (IRQ)
14.1 Introduction
The IRQ module provides two external interrupt inputs: one dedicated IRQ pin and one shared port pin,
PTE3/D–.
14.2 Features
Features of the IRQ module include:
14.3 Functional Description
A logic 0 applied to the external interrupt pin can latch a CPU interrupt request.
structure of the IRQ module.
Interrupt signals on the IRQ pin are latched into the IRQ latch. An interrupt latch remains set until one of
the following actions occurs:
The external interrupt pin is falling-edge-triggered and is software-configurable to be either falling-edge
or low-level-triggered. The MODE bit in the ISCR controls the triggering sensitivity of the IRQ pin.
When the interrupt pin is edge-triggered only, the CPU interrupt request remains set until a vector fetch,
software clear, or reset occurs.
When the interrupt pin is both falling-edge and low-level-triggered, the CPU interrupt request remains set
until both of the following occur:
The vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. As long as
the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE control
bit, thereby clearing the interrupt even if the pin stays low.
Freescale Semiconductor
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Two external interrupt pins, IRQ and PTE3/D–
IRQ interrupt control bits
Programmable edge-only or edge and level interrupt sensitivity
Automatic interrupt acknowledge
Low leakage IRQ pin for external RC wake up input
Selectable internal pullup resistor
Vector fetch — A vector fetch automatically generates an interrupt acknowledge signal that clears
the IRQ latch.
Software clear — Software can clear the interrupt latch by writing to the acknowledge bit in the
interrupt status and control register (ISCR). Writing a logic 1 to the ACK bit clears the IRQ latch.
Reset — A reset automatically clears the interrupt latch.
Vector fetch or software clear
Return of the interrupt pin to logic one
MC68HC908JW32 Data Sheet, Rev. 6
Figure 14-1
shows the
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