MCHC908JW32FAE Freescale Semiconductor, MCHC908JW32FAE Datasheet - Page 141

• Manufacturer Part Number: MCHC908JW32FAE
• Description: IC MCU 32K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908JW32FAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, USB
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 48
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: HC08JW
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, USB
• Number Of Programmable I/os: 29
• Number Of Timers: 2
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

When enabled, the SPI controls data direction of the SPSCK pin regardless of the state of the data
direction register of the shared I/O port.
10.12.4 SS (Slave Select)
The SS pin has various functions depending on the current state of the SPI. For an SPI configured as a
slave, the SS is used to select a slave. For CPHA = 0, the SS is used to define the start of a transmission.
(See
toggled high and low between each byte transmitted for the CPHA = 0 format. However, it can remain low
between transmissions for the CPHA = 1 format. See
When an SPI is configured as a slave, the SS pin is always configured as an input. It cannot be used as
a general-purpose I/O regardless of the state of the MODFEN control bit. However, the MODFEN bit can
still prevent the state of the SS from creating a MODF error. (See
Register.)
When an SPI is configured as a master, the SS input can be used in conjunction with the MODF flag to
prevent multiple masters from driving MOSI and SPSCK. (See
the SS pin to set the MODF flag, the MODFEN bit in the SPSCK register must be set. If the MODFEN bit
is low for an SPI master, the SS pin can be used as a general-purpose I/O under the control of the data
direction register of the shared I/O port. With MODFEN high, it is an input-only pin to the SPI regardless
of the state of the data direction register of the shared I/O port.
The CPU can always read the state of the SS pin by configuring the appropriate pin as an input and
reading the port data register. (See
Freescale Semiconductor
10.5 Transmission
MASTER SS
SPE
MISO/MOSI
A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a
high-impedance state. The slave SPI ignores all incoming SPSCK clocks,
even if it was already in the middle of a transmission.
Note 1. X = Don’t care
0
1
1
1
SLAVE SS
SLAVE SS
CPHA = 0
CPHA = 1
SPMSTR
Formats.) Since it is used to indicate the start of a transmission, the SS must be
X
0
1
1
(1)
MODFEN
Figure 10-12. CPHA/SS Timing
BYTE 1
Table
MC68HC908JW32 Data Sheet, Rev. 6
Table 10-3. SPI Configuration
X
X
0
1
10-3.)
Master without MODF
SPI Configuration
Master with MODF
NOTE
Not enabled
Slave
Figure
BYTE 2
10-12.
10.7.2 Mode Fault
10.13.2 SPI Status and Control
General-purpose I/O;
General-purpose I/O;
State of SS Logic
SS ignored by SPI
SS ignored by SPI
Input-only to SPI
Input-only to SPI
BYTE 3
Error.) For the state of
I/O Signals
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