MCHC908JW32FAE Freescale Semiconductor, MCHC908JW32FAE Datasheet - Page 198

• Manufacturer Part Number: MCHC908JW32FAE
• Description: IC MCU 32K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908JW32FAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, USB
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 48
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: HC08JW
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, USB
• Number Of Programmable I/os: 29
• Number Of Timers: 2
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Computer Operating Properly (COP)
The COP counter is a free-running 6-bit counter preceded by a 12-bit system integration module (SIM)
counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset
after 262,128 or 8176 CGMRCLK cycles, depending on the state of the COP rate select bit, COPRS in
the configuration register. With a 262,128 CGMRCLK cycle overflow option (COPRS = 0), a 4-MHz
external clock source gives a COP timeout period of 66ms. Writing any value to location $FFFF before
an overflow occurs prevents a COP reset by clearing the COP counter and stages 12 through 5 of the
SIM counter.
A COP reset pulls the RST pin low for 32 CGMRCLK cycles and sets the COP bit in the reset status
register (RSR).
In monitor mode, the COP is disabled if the RST pin or the IRQ is held at V
V
16.3 I/O Signals
The following paragraphs describe the signals shown in
16.3.1 CGMRCLK
CGMRCLK is the reference clock output from the OSC module. If a 4-MHz crystal is used, CGMRCLK is
also 4-MHz.
16.3.2 STOP Instruction
The STOP instruction clears the COP prescaler.
16.3.3 COPCTL Write
Writing any value to the COP control register (COPCTL) (see
counter and clears bits 12 through 5 of the SIM counter. Reading the COP control register returns the low
byte of the reset vector.
16.3.4 Power-On Reset
The power-on reset (POR) circuit in the SIM clears the COP prescaler 4096 CGMRCLK cycles after
power-up.
16.3.5 Internal Reset
An internal reset clears the SIM counter and the COP counter.
198
TST
on the RST pin disables the COP.
Service the COP immediately after reset and before entering or after exiting
stop mode to guarantee the maximum time before the first COP counter
overflow.
Place COP clearing instructions in the main program and not in an interrupt
subroutine. Such an interrupt subroutine could keep the COP from
generating a reset even while the main program is not working properly.
MC68HC908JW32 Data Sheet, Rev. 6
NOTE
NOTE
Figure
16.4 COP Control
16-1.
TST
. During the break state,
Register) clears the COP
Freescale Semiconductor