MCHC908JW32FAE Freescale Semiconductor, MCHC908JW32FAE Datasheet - Page 158

• Manufacturer Part Number: MCHC908JW32FAE
• Description: IC MCU 32K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908JW32FAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, USB
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 48
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: HC08JW
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, USB
• Number Of Programmable I/os: 29
• Number Of Timers: 2
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

USB 2.0 FS Module
USBRSTIE — USB RESET Interrupt Mask
RESUMEFIE — Resume Interrupt Mask
SUSPNDIE — Suspend Mode Interrupt Mask
11.5.4 USB Endpoint 0 Control/Status Register (UEP0CSR)
DSIZE[3:0]_OUT — Endpoint 0 Data Size for OUT packet
DSIZE[3:0]_IN — Endpoint 0 Data Size for IN packet
DVALID_IN — Data valid enable bit for IN packet
TFRC_IN — Transfer Complete Flag for IN packet
158
This read/write bit enables a CPU interrupt request when USBRST flag of USB status register
(USBSR) and URSTD bit of configuration register (CONFIG) is set. Reset clears this bit.
This read/write bit enables a CPU interrupt request when the USB bus activity is resumed or
RESUMEF of USB status register (USBSR) is set. Reset clears this bit.
This read/write bit enables a CPU interrupt request when the module entered suspend mode or
SUSPND flag of USB status register (USBSR) is set. Reset clears this bit.
These bits specify the packet size received for the previous valid OUT packet. The bits are read only.
These bits indicates the packet size to be transmitted in response to the next IN packet. The bits are
write only.
This read/write bit indicates the data in the endpoint buffer is valid and ready to send. Setting this bit
triggers the data transmission. The bit will be cleared automatically by hardware when a successful IN
packet transaction occurred or a valid SETUP packet is received. The bit can also be cleared by writing
zero. When the bit is zero, all IN packets to endpoint zero will be responded by NAK. Reset also clears
this bit.
This read/write bit indicates the data in the EP0 buffer is completely transferred to the host. When the
bit is set, all successive IN packet is responded by NAK. Writing zero to clear this bit. Writing one to
the bit has no effect.
1 = CPU interrupt request is enabled when USB reset signal is detected
0 = CPU interrupt request is disabled when USB reset signal is detected
1 = CPU interrupt request is enabled when USB bus activity is resumed
0 = CPU interrupt request is disabled when USB bus activity is resumed
1 = CPU interrupt request is enabled when the module enters suspend mode
0 = CPU interrupt request is disabled when the module enters suspend mode
1 = Data in the EP0 buffer is valid and ready to transmit
0 = Data in the EP0 buffer is not valid
1 = Endpoint data transfer completed
0 = Default status
Address:
Reset:
Read: DSIZE3_OUT DSIZE2_OUT DSIZE1_OUT DSIZE0_OUT
Write:
DSIZE3_IN
$0054
Bit 7
0
Figure 11-6. USB Endpoint 0 Control/Status Register
DSIZE2_IN
6
0
MC68HC908JW32 Data Sheet, Rev. 6
DSIZE1_IN
5
0
DSIZE0_IN
4
0
DVALID_IN
3
0
TFRC_IN
2
0
DVALID_OUT
1
0
Freescale Semiconductor
TFRC_OUT
Bit 0
0