MCHC908JW32FAE Freescale Semiconductor, MCHC908JW32FAE Datasheet - Page 90

• Manufacturer Part Number: MCHC908JW32FAE
• Description: IC MCU 32K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908JW32FAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, USB
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 48
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: HC08JW
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, USB
• Number Of Programmable I/os: 29
• Number Of Timers: 2
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

System Integration Module (SIM)
6.7 SIM Registers
The SIM has three memory-mapped registers:
6.7.1 SIM Break Status Register
The SIM break status register (SBSR) contains a flag to indicate that a break caused an exit from stop
mode or wait mode. This register is used only in emulation mode.
SBSW — Break Wait Bit
6.7.2 SIM Reset Status Register
This register contains six flags that show the source of the last reset provided all previous reset status
bits have been cleared. Clear the SIM reset status register by reading it. A power-on reset sets the POR
bit and clears all other bits in the register.
The register is initialized on power up with the POR bit set and all other bits cleared. During a POR or any
other internal reset, the RST pin is pulled low. After the pin is released, it will be sampled 32 CGMXCLK
cycles later. If the pin is not above V
other bits are set.
POR — Power-On Reset Bit
90
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•
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SBSW can be read within the break interrupt routine. The user can modify the return address on the
stack by subtracting 1 from it.
1 = Wait mode was exited by break interrupt
0 = Wait mode was not exited by break interrupt
1 = Last reset caused by POR circuit
0 = Read of SRSR
SIM Break Status Register
SIM Reset Status Register
SIM Break Flag Control Register
Note: Writing a logic 0 clears SBSW.
Address:
Address:
Reset:
Reset:
Read:
Read:
Write:
Write:
$FE00
$FE01
POR
Bit 7
Bit 7
R
1
Figure 6-20. SIM Break Status Register (SBSR)
Figure 6-21. SIM Reset Status Register (SRSR)
= Unimplemented
PIN
R
6
6
0
(SBSR) — $FE00
(SRSR) — $FE01
MC68HC908JW32 Data Sheet, Rev. 6
IH
at this time, then the PIN bit may be set, in addition to whatever
(SBFCR) — $FE03
COP
R
R
5
5
0
= Reserved
ILOP
R
4
4
0
ILAD
R
3
3
0
USB
R
2
2
0
SBSW
Note
LVI
1
0
1
0
Freescale Semiconductor
Bit 0
Bit 0
R
0
0